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Mon, 06 Nov 2023 10:51:15 -0800 (PST) Received: from draig.lan (localhost [IPv6:::1]) by draig.lan (Postfix) with ESMTP id E5E1C6574F; Mon, 6 Nov 2023 18:51:12 +0000 (GMT) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , =?utf-8?q?Marc-Andr=C3=A9_Lureau?= , Laurent Vivier , =?utf-8?q?Alex_Benn=C3=A9e?= , Mahmoud Mandour , Cleber Rosa , Wainer dos Santos Moschetta , Paolo Bonzini , Thomas Huth , Beraldo Leal , Alexandre Iooss , John Snow , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Chris Wulff , Marek Vasut , Richard Henderson Subject: [PATCH 05/22] target/arm: hide aliased MIDR from gdbstub Date: Mon, 6 Nov 2023 18:50:55 +0000 Message-Id: <20231106185112.2755262-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231106185112.2755262-1-alex.bennee@linaro.org> References: <20231106185112.2755262-1-alex.bennee@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::12e; envelope-from=alex.bennee@linaro.org; helo=mail-lf1-x12e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is just a constant alias register with the same value as the "other" MIDR so it serves no purpose being presented to gdbstub. Signed-off-by: Alex Bennée Message-Id: <20231103195956.1998255-6-alex.bennee@linaro.org> Reviewed-by: Peter Maydell --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 104f9378b4..a681bcba62 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8993,7 +8993,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .type = ARM_CP_CONST, .resetvalue = cpu->revidr }, }; ARMCPRegInfo id_v8_midr_alias_cp_reginfo = { - .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST, + .name = "MIDR", .type = ARM_CP_ALIAS | ARM_CP_CONST | ARM_CP_NO_GDB, .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 4, .access = PL1_R, .resetvalue = cpu->midr };