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[176.131.220.199]) by smtp.gmail.com with ESMTPSA id o13-20020a05600c4fcd00b0040588d85b3asm11817685wmq.15.2023.11.06.03.05.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 06 Nov 2023 03:05:37 -0800 (PST) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: kvm@vger.kernel.org, qemu-s390x@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Richard Henderson , Stafford Horne Subject: [PULL 17/60] target/openrisc: Declare QOM definitions in 'cpu-qom.h' Date: Mon, 6 Nov 2023 12:02:49 +0100 Message-ID: <20231106110336.358-18-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231106110336.358-1-philmd@linaro.org> References: <20231106110336.358-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22d; envelope-from=philmd@linaro.org; helo=mail-lj1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Add a comment clarifying that in the header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-Id: <20231013140116.255-11-philmd@linaro.org> --- target/openrisc/cpu-qom.h | 22 ++++++++++++++++++++++ target/openrisc/cpu.h | 10 +--------- 2 files changed, 23 insertions(+), 9 deletions(-) create mode 100644 target/openrisc/cpu-qom.h diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h new file mode 100644 index 0000000000..1ba9fb0a4c --- /dev/null +++ b/target/openrisc/cpu-qom.h @@ -0,0 +1,22 @@ +/* + * QEMU OpenRISC CPU QOM header (target agnostic) + * + * Copyright (c) 2011-2012 Jia Liu + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_OPENRISC_CPU_QOM_H +#define QEMU_OPENRISC_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_OPENRISC_CPU "or1k-cpu" + +OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) + +#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU +#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX + +#endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 29cda7279c..dedeb89f8e 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,17 +20,12 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#include "hw/core/cpu.h" -#include "qom/object.h" #define TCG_GUEST_DEFAULT_MO (0) -#define TYPE_OPENRISC_CPU "or1k-cpu" - -OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) - /** * OpenRISCCPUClass: * @parent_realize: The parent class' realize handler. @@ -304,7 +299,6 @@ struct ArchCPU { CPUOpenRISCState env; }; - void cpu_openrisc_list(void); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -339,8 +333,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #endif -#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU -#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU #include "exec/cpu-all.h"