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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id c10-20020a170902c1ca00b001c0cb2aa2easm1628267plc.121.2023.11.03.10.38.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Nov 2023 10:38:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH 08/22] target/sparc: Use i128 for FqTOs, FqTOi Date: Fri, 3 Nov 2023 10:38:27 -0700 Message-Id: <20231103173841.33651-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231103173841.33651-1-richard.henderson@linaro.org> References: <20231103173841.33651-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/helper.h | 4 ++-- target/sparc/fop_helper.c | 8 ++++---- target/sparc/translate.c | 7 ++++--- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/sparc/helper.h b/target/sparc/helper.h index 0a030fc908..e770107eb0 100644 --- a/target/sparc/helper.h +++ b/target/sparc/helper.h @@ -98,13 +98,13 @@ DEF_HELPER_FLAGS_2(fxtoq, TCG_CALL_NO_RWG, void, env, s64) #endif DEF_HELPER_FLAGS_2(fdtos, TCG_CALL_NO_RWG, f32, env, f64) DEF_HELPER_FLAGS_2(fstod, TCG_CALL_NO_RWG, f64, env, f32) -DEF_HELPER_FLAGS_1(fqtos, TCG_CALL_NO_RWG, f32, env) +DEF_HELPER_FLAGS_2(fqtos, TCG_CALL_NO_RWG, f32, env, i128) DEF_HELPER_FLAGS_2(fstoq, TCG_CALL_NO_RWG, void, env, f32) DEF_HELPER_FLAGS_1(fqtod, TCG_CALL_NO_RWG, f64, env) DEF_HELPER_FLAGS_2(fdtoq, TCG_CALL_NO_RWG, void, env, f64) DEF_HELPER_FLAGS_2(fstoi, TCG_CALL_NO_RWG, s32, env, f32) DEF_HELPER_FLAGS_2(fdtoi, TCG_CALL_NO_RWG, s32, env, f64) -DEF_HELPER_FLAGS_1(fqtoi, TCG_CALL_NO_RWG, s32, env) +DEF_HELPER_FLAGS_2(fqtoi, TCG_CALL_NO_RWG, s32, env, i128) #ifdef TARGET_SPARC64 DEF_HELPER_FLAGS_2(fstox, TCG_CALL_NO_RWG, s64, env, f32) DEF_HELPER_FLAGS_2(fdtox, TCG_CALL_NO_RWG, s64, env, f64) diff --git a/target/sparc/fop_helper.c b/target/sparc/fop_helper.c index ceb64d802f..657a14575d 100644 --- a/target/sparc/fop_helper.c +++ b/target/sparc/fop_helper.c @@ -180,9 +180,9 @@ float64 helper_fstod(CPUSPARCState *env, float32 src) return float32_to_float64(src, &env->fp_status); } -float32 helper_fqtos(CPUSPARCState *env) +float32 helper_fqtos(CPUSPARCState *env, Int128 src) { - return float128_to_float32(QT1, &env->fp_status); + return float128_to_float32(f128_in(src), &env->fp_status); } void helper_fstoq(CPUSPARCState *env, float32 src) @@ -211,9 +211,9 @@ int32_t helper_fdtoi(CPUSPARCState *env, float64 src) return float64_to_int32_round_to_zero(src, &env->fp_status); } -int32_t helper_fqtoi(CPUSPARCState *env) +int32_t helper_fqtoi(CPUSPARCState *env, Int128 src) { - return float128_to_int32_round_to_zero(QT1, &env->fp_status); + return float128_to_int32_round_to_zero(f128_in(src), &env->fp_status); } #ifdef TARGET_SPARC64 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 437f54ff19..34a774c8ef 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4692,8 +4692,9 @@ static bool do_env_qq(DisasContext *dc, arg_r_r *a, TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) static bool do_env_fq(DisasContext *dc, arg_r_r *a, - void (*func)(TCGv_i32, TCGv_env)) + void (*func)(TCGv_i32, TCGv_env, TCGv_i128)) { + TCGv_i128 src; TCGv_i32 dst; if (gen_trap_ifnofpu(dc)) { @@ -4704,9 +4705,9 @@ static bool do_env_fq(DisasContext *dc, arg_r_r *a, } gen_op_clear_ieee_excp_and_FTT(); - gen_op_load_fpr_QT1(QFPREG(a->rs)); + src = gen_load_fpr_Q(dc, a->rs); dst = tcg_temp_new_i32(); - func(dst, tcg_env); + func(dst, tcg_env, src); gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); gen_store_fpr_F(dc, a->rd, dst); return advance_pc(dc);