From patchwork Thu Nov 2 01:28:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 740351 Delivered-To: patch@linaro.org Received: by 2002:a5d:538f:0:b0:32d:baff:b0ca with SMTP id d15csp594004wrv; Wed, 1 Nov 2023 18:33:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF2xD4XB9DaaJcvpJNzgHsK+/jVWbKHjaf5WcXBqq94uig/8aJGmH16MY9jdw46i8lXaT73 X-Received: by 2002:ad4:5bce:0:b0:66d:2fda:c9e0 with SMTP id t14-20020ad45bce000000b0066d2fdac9e0mr21539629qvt.61.1698888825000; Wed, 01 Nov 2023 18:33:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698888824; cv=none; d=google.com; s=arc-20160816; b=D5Y+AFx3NhbyI6/+6wLDjxLb0L61hWlrM2Wj/5t2yG6ARom4UTMxHRUSAjMMGZqRej Zs/YKiEsXzqvMXzrseARMIzdo+MQ6yZWV646+h85rdhLK9xxSDOT5yN7c3GeA8M1WYwk wWBwn7TMLNU1tjynJbNpAkrg7VHu61XBa48x0gHtnGZeQ11slpWI2KfpfoFpF+hHhQFP C4Dl8B6ZaJb9dCXX40HYsFbStbvNHRSX5En4xdZNys9+k5zbFTQL6K7kfwD1tNSO+9Gx xDJv/r/hackvRxq8EbI1SRdbEUfmiQC/zyaCtUMmg9SiCJ8pV9C7M5489HYxcHdUdgS1 zcSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2BJlcx9oSMgaomOh7sPzTCOyXOzihSFEWq7bL9QPBTQ=; fh=f2WZoDMBYjCKWIIOoPI+rQtxlv4fmOm4u+dLdQLqpOk=; b=0ck0baGiby8dREhla+JgXL3GNnXs0P6BdYIliRZggaw+9P+PCW4z23kA9eqZCd+5Qi wUgJejI5tKMSH8MwA4v2r8lGqLIt/bReonQtfhrD6yN2U5Gdqn5dVBimOQThp0fMy9Ca kLZMUO3PfUC4PFKGml4jQnPM/S27ljD9XhS7GdikRhhs7z5fBuLeCeWzuWiGiO+5Cclx DJ3JgBSOUZRjN6Fuzx04euB4dHuS1dxhjWO3VJlEtgBPphOhTM5A9D9sAx5iICopdseW p/EkKQCWJEh4Bi5gnfCu7TmKw6tlkTjIdSd6VkQqTrQDb0gkrw7+adQX6dhiteuf7V6H Jl7Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B+JQs8re; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ef12-20020a0562140a6c00b006238ad6d2d2si3697229qvb.577.2023.11.01.18.33.44 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 01 Nov 2023 18:33:44 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B+JQs8re; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qyMXm-0005kV-1G; Wed, 01 Nov 2023 21:30:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qyMXZ-0005Xd-ON for qemu-devel@nongnu.org; Wed, 01 Nov 2023 21:30:33 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qyMXU-0001VC-8x for qemu-devel@nongnu.org; Wed, 01 Nov 2023 21:30:32 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-6b87c1edfd5so439726b3a.1 for ; Wed, 01 Nov 2023 18:30:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698888625; x=1699493425; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2BJlcx9oSMgaomOh7sPzTCOyXOzihSFEWq7bL9QPBTQ=; b=B+JQs8reI4GrYaj4IioPFzXB1LmosxX5bqNnYj7Kgm3Xn2innnYz7yI1DwA5eUO8Ye Jkw2AMIlbTsRk+epizx/2N3XdWXVWivSusTeX2bhy9DUTzSX4UA90uILKMbXabrEk7Li GZqtJ5jDpI7auH91n8sBpuMKb1btYPlWqEKeRk0QS4W04iuK/uy2EZle6nqMasTsv1gH eB3E0QeS7x8pqXNvIAqRv+Bi4tkiiN+bPCG+r1veNAN3SDbFCpiqdSez6naXJPOEvhue 9ObhQi/Q+CpCdQZSYE75C1doRGT9P+6ViFfFj1Gjoz/ngw6HEgelHMbCG4qRfRFlOuOe YwIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698888625; x=1699493425; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2BJlcx9oSMgaomOh7sPzTCOyXOzihSFEWq7bL9QPBTQ=; b=DiDlfs2pTnvzfWC85pDJp52rAOrZuAHRSZireitqPfkGzA8zzr8gBtpUyHYTjxFbiw bQRyPhvx5MuPOJD/XNUcIWO1HWQSxjqo0M5ujaffbPsPufUbeCfehJ2y/sRF6RZFa7EN UK6XiYgMuvD1kDzm+r8nmj3ROaP3mBoBuWM4azz/fax2g87saUZkh8y4VicW268yMxcE skz/pyoaAFtu3YdU905XzhpvHv1sl8uBQyvWYrw+5TW2I6oQZI/Qes6Y2LfSUsgvskG9 hGvQ3kUycBUf8quZ049q72Kdxd+ATgTaNkSzh4rckZ3bhNHV6cj3Kb4p6Wp+eE8oGmkI zwfg== X-Gm-Message-State: AOJu0Yxu+kHhZvJE+3mFkEsJSgDrVCk7M+Lout1X4IdWA705ukqvtDYL KcKWWCcsWYMop8VojGDKE8SlVYUFty6mhL6wtMI= X-Received: by 2002:a05:6a00:9a6:b0:6be:18a9:8f60 with SMTP id u38-20020a056a0009a600b006be18a98f60mr18378034pfg.16.1698888624315; Wed, 01 Nov 2023 18:30:24 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r23-20020aa78457000000b006979f70fdd5sm1784191pfn.219.2023.11.01.18.30.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 18:30:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v3 08/88] tcg: Improve expansion of deposit into a constant Date: Wed, 1 Nov 2023 18:28:56 -0700 Message-Id: <20231102013016.369010-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231102013016.369010-1-richard.henderson@linaro.org> References: <20231102013016.369010-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Generalize tcg_gen_deposit_z_* from 0 to any constant. Use this to automatically simplify tcg_gen_deposit_*. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 295 ++++++++++++++++++++++++++++++--------------------- 1 file changed, 174 insertions(+), 121 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index e305260099..e6bf942106 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -603,6 +603,70 @@ void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) } } +static void tcg_gen_deposit_i_i32(TCGv_i32 ret, uint32_t i, TCGv_i32 arg, + unsigned int ofs, unsigned int len) +{ + i = deposit32(i, ofs, len, 0); + + if (ofs + len == 32) { + tcg_gen_shli_i32(ret, arg, ofs); + goto finish; + } + if (ofs == 0) { + tcg_gen_andi_i32(ret, arg, (1u << len) - 1); + goto finish; + } + if (TCG_TARGET_HAS_deposit_i32 + && TCG_TARGET_deposit_i32_valid(ofs, len)) { + tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, + tcg_constant_i32(i), arg, ofs, len); + return; + } + + /* + * To help two-operand hosts we prefer to zero-extend first, + * which allows ARG to stay live. + */ + switch (len) { + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_ext16u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_ext8u_i32(ret, arg); + tcg_gen_shli_i32(ret, ret, ofs); + goto finish; + } + break; + } + /* Otherwise prefer zero-extension over AND for code size. */ + switch (ofs + len) { + case 16: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext16u_i32(ret, ret); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_shli_i32(ret, arg, ofs); + tcg_gen_ext8u_i32(ret, ret); + goto finish; + } + break; + } + tcg_gen_andi_i32(ret, arg, (1u << len) - 1); + tcg_gen_shli_i32(ret, ret, ofs); + + finish: + tcg_gen_ori_i32(ret, ret, i); +} + void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, unsigned int ofs, unsigned int len) { @@ -619,6 +683,14 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, tcg_gen_mov_i32(ret, arg2); return; } + + /* Deposit of a value into a constant. */ + ts = tcgv_i32_temp(arg1); + if (ts->kind == TEMP_CONST) { + tcg_gen_deposit_i_i32(ret, ts->val, arg2, ofs, len); + return; + } + if (TCG_TARGET_HAS_deposit_i32 && TCG_TARGET_deposit_i32_valid(ofs, len)) { tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, arg1, arg2, ofs, len); return; @@ -673,53 +745,7 @@ void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, tcg_debug_assert(len <= 32); tcg_debug_assert(ofs + len <= 32); - if (ofs + len == 32) { - tcg_gen_shli_i32(ret, arg, ofs); - } else if (ofs == 0) { - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i32 - && TCG_TARGET_deposit_i32_valid(ofs, len)) { - TCGv_i32 zero = tcg_constant_i32(0); - tcg_gen_op5ii_i32(INDEX_op_deposit_i32, ret, zero, arg, ofs, len); - } else { - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_ext16u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_ext8u_i32(ret, arg); - tcg_gen_shli_i32(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 16: - if (TCG_TARGET_HAS_ext16u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext16u_i32(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i32) { - tcg_gen_shli_i32(ret, arg, ofs); - tcg_gen_ext8u_i32(ret, ret); - return; - } - break; - } - tcg_gen_andi_i32(ret, arg, (1u << len) - 1); - tcg_gen_shli_i32(ret, ret, ofs); - } + tcg_gen_deposit_i_i32(ret, 0, arg, ofs, len); } void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, @@ -2238,6 +2264,98 @@ void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) } } +static void tcg_gen_deposit_i_i64(TCGv_i64 ret, uint64_t i, TCGv_i64 arg, + unsigned int ofs, unsigned int len) +{ + i = deposit64(i, ofs, len, 0); + + if (ofs + len == 64) { + tcg_gen_shli_i64(ret, arg, ofs); + goto finish; + } + if (ofs == 0) { + tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); + goto finish; + } + if (TCG_TARGET_HAS_deposit_i64 + && TCG_TARGET_deposit_i64_valid(ofs, len)) { + tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, + tcg_constant_i64(i), arg, ofs, len); + return; + } + + if (TCG_TARGET_REG_BITS == 32) { + if (ofs >= 32) { + tcg_gen_deposit_i_i32(TCGV_HIGH(ret), i >> 32, + TCGV_LOW(arg), ofs - 32, len); + tcg_gen_movi_i32(TCGV_LOW(ret), i); + return; + } + if (ofs + len <= 32) { + tcg_gen_deposit_i_i32(TCGV_LOW(ret), i, TCGV_LOW(arg), ofs, len); + tcg_gen_movi_i32(TCGV_HIGH(ret), i >> 32); + return; + } + } + + /* + * To help two-operand hosts we prefer to zero-extend first, + * which allows ARG to stay live. + */ + switch (len) { + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_ext32u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_ext16u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_ext8u_i64(ret, arg); + tcg_gen_shli_i64(ret, ret, ofs); + goto finish; + } + break; + } + /* Otherwise prefer zero-extension over AND for code size. */ + switch (ofs + len) { + case 32: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext32u_i64(ret, ret); + goto finish; + } + break; + case 16: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext16u_i64(ret, ret); + goto finish; + } + break; + case 8: + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_shli_i64(ret, arg, ofs); + tcg_gen_ext8u_i64(ret, ret); + goto finish; + } + break; + } + tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); + tcg_gen_shli_i64(ret, ret, ofs); + + finish: + tcg_gen_ori_i64(ret, ret, i); +} + void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, unsigned int ofs, unsigned int len) { @@ -2254,6 +2372,14 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, tcg_gen_mov_i64(ret, arg2); return; } + + /* Deposit of a value into a constant. */ + ts = tcgv_i64_temp(arg1); + if (ts->kind == TEMP_CONST) { + tcg_gen_deposit_i_i64(ret, ts->val, arg2, ofs, len); + return; + } + if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(ofs, len)) { tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, arg1, arg2, ofs, len); return; @@ -2323,80 +2449,7 @@ void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, tcg_debug_assert(len <= 64); tcg_debug_assert(ofs + len <= 64); - if (ofs + len == 64) { - tcg_gen_shli_i64(ret, arg, ofs); - } else if (ofs == 0) { - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - } else if (TCG_TARGET_HAS_deposit_i64 - && TCG_TARGET_deposit_i64_valid(ofs, len)) { - TCGv_i64 zero = tcg_constant_i64(0); - tcg_gen_op5ii_i64(INDEX_op_deposit_i64, ret, zero, arg, ofs, len); - } else { - if (TCG_TARGET_REG_BITS == 32) { - if (ofs >= 32) { - tcg_gen_deposit_z_i32(TCGV_HIGH(ret), TCGV_LOW(arg), - ofs - 32, len); - tcg_gen_movi_i32(TCGV_LOW(ret), 0); - return; - } - if (ofs + len <= 32) { - tcg_gen_deposit_z_i32(TCGV_LOW(ret), TCGV_LOW(arg), ofs, len); - tcg_gen_movi_i32(TCGV_HIGH(ret), 0); - return; - } - } - /* To help two-operand hosts we prefer to zero-extend first, - which allows ARG to stay live. */ - switch (len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_ext32u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_ext16u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_ext8u_i64(ret, arg); - tcg_gen_shli_i64(ret, ret, ofs); - return; - } - break; - } - /* Otherwise prefer zero-extension over AND for code size. */ - switch (ofs + len) { - case 32: - if (TCG_TARGET_HAS_ext32u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext32u_i64(ret, ret); - return; - } - break; - case 16: - if (TCG_TARGET_HAS_ext16u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext16u_i64(ret, ret); - return; - } - break; - case 8: - if (TCG_TARGET_HAS_ext8u_i64) { - tcg_gen_shli_i64(ret, arg, ofs); - tcg_gen_ext8u_i64(ret, ret); - return; - } - break; - } - tcg_gen_andi_i64(ret, arg, (1ull << len) - 1); - tcg_gen_shli_i64(ret, ret, ofs); - } + tcg_gen_deposit_i_i64(ret, 0, arg, ofs, len); } void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,