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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r23-20020aa78457000000b006979f70fdd5sm1784191pfn.219.2023.11.01.18.30.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 18:30:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v3 07/88] tcg: Improve expansion of deposit of constant Date: Wed, 1 Nov 2023 18:28:55 -0700 Message-Id: <20231102013016.369010-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231102013016.369010-1-richard.henderson@linaro.org> References: <20231102013016.369010-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The extract2 expansion is too difficult for the optimizer to simplify. If we have an immediate input, use and+or instead, skipping the and if the field becomes all 1's. Signed-off-by: Richard Henderson --- tcg/tcg-op.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 828eb9ee46..e305260099 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -608,6 +608,7 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, { uint32_t mask; TCGv_i32 t1; + TCGTemp *ts; tcg_debug_assert(ofs < 32); tcg_debug_assert(len > 0); @@ -623,6 +624,19 @@ void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, return; } + /* Deposit of a constant into a value. */ + ts = tcgv_i32_temp(arg2); + if (ts->kind == TEMP_CONST) { + uint32_t mask0 = deposit32(-1, ofs, len, 0); + uint32_t maski = deposit32(0, ofs, len, ts->val); + + if (mask0 != ~maski) { + tcg_gen_andi_i32(ret, arg1, mask0); + } + tcg_gen_ori_i32(ret, ret, maski); + return; + } + t1 = tcg_temp_ebb_new_i32(); if (TCG_TARGET_HAS_extract2_i32) { @@ -2229,6 +2243,7 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, { uint64_t mask; TCGv_i64 t1; + TCGTemp *ts; tcg_debug_assert(ofs < 64); tcg_debug_assert(len > 0); @@ -2244,6 +2259,19 @@ void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, return; } + /* Deposit of a constant into a value. */ + ts = tcgv_i64_temp(arg2); + if (ts->kind == TEMP_CONST) { + uint64_t mask0 = deposit64(-1, ofs, len, 0); + uint64_t maski = deposit64(0, ofs, len, ts->val); + + if (mask0 != ~maski) { + tcg_gen_andi_i64(ret, arg1, mask0); + } + tcg_gen_ori_i64(ret, ret, maski); + return; + } + if (TCG_TARGET_REG_BITS == 32) { if (ofs >= 32) { tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),