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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id r23-20020aa78457000000b006979f70fdd5sm1784191pfn.219.2023.11.01.18.30.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 18:30:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH v3 30/88] target/hppa: Mask inputs in copy_iaoq_entry Date: Wed, 1 Nov 2023 18:29:18 -0700 Message-Id: <20231102013016.369010-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231102013016.369010-1-richard.henderson@linaro.org> References: <20231102013016.369010-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Ensure that the destination is always a valid GVA offset. Signed-off-by: Richard Henderson --- target/hppa/translate.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index c2db2782f4..cf05d8b6e4 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -720,10 +720,22 @@ static target_ureg gva_offset_mask(DisasContext *ctx) static void copy_iaoq_entry(DisasContext *ctx, TCGv_reg dest, target_ureg ival, TCGv_reg vval) { - if (unlikely(ival == -1)) { + target_ureg mask = gva_offset_mask(ctx); + + if (ival != -1) { + tcg_gen_movi_reg(dest, ival & mask); + return; + } + tcg_debug_assert(vval != NULL); + + /* + * We know that the IAOQ is already properly masked. + * This optimization is primarily for "iaoq_f = iaoq_b". + */ + if (vval == cpu_iaoq_f || vval == cpu_iaoq_b) { tcg_gen_mov_reg(dest, vval); } else { - tcg_gen_movi_reg(dest, ival); + tcg_gen_andi_reg(dest, vval, mask); } }