From patchwork Thu Oct 26 00:14:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 738239 Delivered-To: patch@linaro.org Received: by 2002:adf:f842:0:b0:32d:baff:b0ca with SMTP id d2csp555883wrq; Wed, 25 Oct 2023 17:28:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEms9yBdeinVwfUVzcETs2SBsas46ojRjgPYaVr/kfQLTHqm8JixXji/lzlWyjKBb5aE2W8 X-Received: by 2002:a17:907:360d:b0:9be:6ff7:1287 with SMTP id bk13-20020a170907360d00b009be6ff71287mr14022305ejc.57.1698280127102; Wed, 25 Oct 2023 17:28:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698280127; cv=none; d=google.com; s=arc-20160816; b=sWAVlAYVkvc3bexSV+DO1Hu5FSW8pDuttTIdZdCYsPGawbQ5bkoswe4kjd+6tilUw+ HhO0fMtUMHpkjYz/MeNQS6U/Mhxxs9tQRZweEMLG2+1G79p6qSOlP22Ff+89GRgk/ENW ZfXD8MW0oPyus2BBs3wXQAbFsgjpigqPYpwh0+Xb5ms4cHFFB9GDauS7fdgxQTZ1lPmo mAeLlMxqLGTVTzDoqeWrd7LPg0pLeteEhI2pyDA+BHD+i1UKBHpqPX2cIwAkmeEF983k EzLTKBRMQUL4XzwD/DjTK4jL+7BrEb7Jb32EcvgfOyEMvbQ8quufmB9MyLTL5JT0+lKw qVbQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=wPe+9mvEGZleEWGbkTca1tKdwjbDs6ccbxNSMhBGMcE=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=pIuo8MjjBFp67pzM/4KHsrAq0VxPHSRkDl7vlnoSoFw9KOZn0YGMbE/LXTB4x8WK8P pR5Qj57WqR8z3mEea41Ko1nrhqefTWUM99SzwNGDk4gXkvCTM+a4qUaB7JiVpirulukf DVPUW2LqCE18lGYAHl+cOO54H6e+ojjBtKe14dRQ3sadsiDtU8xgKCwyOYi/nNHOhGqL Ce40KpnV/HJdGpoL5C/kwAcUQKqQyDrS6m19i//hTpjflOtkifA05T6IBsJqkhQ9GPJ3 tfzy8dFbOUjAG19R2eMCR9DXtwFWyImkfGRayI6Y4oECMG9oLriCKIb+G8xGoyWg9bFD ktAQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u4WrU2RD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id x14-20020a170906148e00b009ad84cca643si5958772ejc.808.2023.10.25.17.28.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 25 Oct 2023 17:28:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u4WrU2RD; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qvo6d-00022b-JN; Wed, 25 Oct 2023 20:20:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qvo6E-000159-RC for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:46 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qvo5v-0006bu-0d for qemu-devel@nongnu.org; Wed, 25 Oct 2023 20:19:46 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1c9e072472bso2235995ad.2 for ; Wed, 25 Oct 2023 17:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1698279566; x=1698884366; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=wPe+9mvEGZleEWGbkTca1tKdwjbDs6ccbxNSMhBGMcE=; b=u4WrU2RDOIOiLKOCL9ymNOTtSaaE6QadfzrVtAz11IRGjoq975nv52aYZFyo/jeEqJ osBcDnMMpkOaCcJQK4ReNNzIvdPQD5cwcwXQDxGIibwgPqhcEfjI4ex8cDZQUpYAWjCq sehthAdcw/xLMf7a3p48Qn1SVDyycQ5ue3GQllhRoZC4a1hzWfayfwsy9VmTP9w55RTk 7HAMXTDJf64bvoq3sEE0+Wlrk9AIIH7VxnZ8uqlN1NYSw405AKnaI9ttuP4pqUqLCU7j zd2mNr/XCmPLXBCUCoxNLrOpvJkZopXKrtnkLvVOSf2o3IzADAJYy63npphFNwLn0Bdq xVaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1698279566; x=1698884366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wPe+9mvEGZleEWGbkTca1tKdwjbDs6ccbxNSMhBGMcE=; b=rfm8aC2XdeQsfdfK7CgqMfP90rq2f5/0MRBoJiikSDn5XyQCE19XosiPrwl/QPT1NR NBD0Bf19nYTsvsn7XCEb3hNst9GPXcswx8/hM+6O0LoqWF/SpR2qrr0yKAqf/gwzFqxy KjhulbPA7ynfRMRdXaUaDLcO5EPTjfvSUihts2M33uv7BfAJPG2nSPfvcW8mQWSEUBpt VMbi2jRMGn/bq/GSu3U1QoDFfG67uiHfnqq7K8d57qoTQayz9ylajiBYO7qtY1NWuOlS bCq3PXESW+I1dkOQEYXa9XdCXS9L5bgPgkbfnACOsvzI0W34uCnGINNsdxkV7o4W9Xh6 IOpw== X-Gm-Message-State: AOJu0Yw72kdvqIboRt2ZGxZdYt2xCOJEbCqlPk3ruZ2jXFUPBNEoo+Wv sdweBJSmo/ukZjQ2Es50b28+NLzjxR+D0GKEfmA= X-Received: by 2002:a17:903:11c5:b0:1c7:23c9:a7e1 with SMTP id q5-20020a17090311c500b001c723c9a7e1mr16159020plh.26.1698279565651; Wed, 25 Oct 2023 17:19:25 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jh1-20020a170903328100b001c5fc291ef9sm9754655plb.209.2023.10.25.17.19.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:19:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 25/29] tcg/s390x: Support TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:14:29 -0700 Message-Id: <20231026001542.1141412-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 127 +++++++++++++++++++++++++------------ 1 file changed, 88 insertions(+), 39 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index fbee43d3b0..ef3cb87e9f 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -111,6 +111,9 @@ typedef enum S390Opcode { RI_OILH = 0xa50a, RI_OILL = 0xa50b, RI_TMLL = 0xa701, + RI_TMLH = 0xa700, + RI_TMHL = 0xa703, + RI_TMHH = 0xa702, RIEb_CGRJ = 0xec64, RIEb_CLGRJ = 0xec65, @@ -403,10 +406,15 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) #define S390_CC_NEVER 0 #define S390_CC_ALWAYS 15 +#define S390_TM_EQ 8 /* CC == 0 */ +#define S390_TM_NE 7 /* CC in {1,2,3} */ + /* Condition codes that result from a COMPARE and COMPARE LOGICAL. */ -static const uint8_t tcg_cond_to_s390_cond[] = { +static const uint8_t tcg_cond_to_s390_cond[16] = { [TCG_COND_EQ] = S390_CC_EQ, [TCG_COND_NE] = S390_CC_NE, + [TCG_COND_TSTEQ] = S390_CC_EQ, + [TCG_COND_TSTNE] = S390_CC_NE, [TCG_COND_LT] = S390_CC_LT, [TCG_COND_LE] = S390_CC_LE, [TCG_COND_GT] = S390_CC_GT, @@ -420,9 +428,11 @@ static const uint8_t tcg_cond_to_s390_cond[] = { /* Condition codes that result from a LOAD AND TEST. Here, we have no unsigned instruction variation, however since the test is vs zero we can re-map the outcomes appropriately. */ -static const uint8_t tcg_cond_to_ltr_cond[] = { +static const uint8_t tcg_cond_to_ltr_cond[16] = { [TCG_COND_EQ] = S390_CC_EQ, [TCG_COND_NE] = S390_CC_NE, + [TCG_COND_TSTEQ] = S390_CC_ALWAYS, + [TCG_COND_TSTNE] = S390_CC_NEVER, [TCG_COND_LT] = S390_CC_LT, [TCG_COND_LE] = S390_CC_LE, [TCG_COND_GT] = S390_CC_GT, @@ -843,6 +853,9 @@ static const S390Opcode oi_insns[4] = { static const S390Opcode lif_insns[2] = { RIL_LLILF, RIL_LLIHF, }; +static const S390Opcode tm_insns[4] = { + RI_TMLL, RI_TMLH, RI_TMHL, RI_TMHH +}; /* load a register with an immediate value */ static void tcg_out_movi(TCGContext *s, TCGType type, @@ -1203,6 +1216,40 @@ static int tgen_cmp2(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, TCGCond inv_c = tcg_invert_cond(c); S390Opcode op; + if (is_tst_cond(c)) { + tcg_debug_assert(!need_carry); + + if (c2const) { + int i; + + if (type == TCG_TYPE_I32) { + c2 = (uint32_t)c2; + } + + i = is_const_p16(c2); + if (i >= 0) { + tcg_out_insn_RI(s, tm_insns[i], r1, c2 >> (i * 16)); + *inv_cc = TCG_COND_TSTEQ ? S390_TM_NE : S390_TM_EQ; + return *inv_cc ^ 15; + } + + if (risbg_mask(c2)) { + tgen_andi_risbg(s, TCG_REG_R0, r1, c2); + goto exit; + } + + tcg_out_movi(s, type, TCG_REG_R0, c2); + c2 = TCG_REG_R0; + } + + if (type == TCG_TYPE_I32) { + tcg_out_insn(s, RRFa, NRK, TCG_REG_R0, r1, c2); + } else { + tcg_out_insn(s, RRFa, NGRK, TCG_REG_R0, r1, c2); + } + goto exit; + } + if (c2const) { if (c2 == 0) { if (!(is_unsigned && need_carry)) { @@ -1516,46 +1563,49 @@ static void tgen_brcond(TCGContext *s, TCGType type, TCGCond c, TCGReg r1, TCGArg c2, int c2const, TCGLabel *l) { int cc; - bool is_unsigned = is_unsigned_cond(c); - bool in_range; - S390Opcode opc; - cc = tcg_cond_to_s390_cond[c]; + if (!is_tst_cond(c)) { + bool is_unsigned = is_unsigned_cond(c); + bool in_range; + S390Opcode opc; - if (!c2const) { - opc = (type == TCG_TYPE_I32 - ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) - : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); - tgen_compare_branch(s, opc, cc, r1, c2, l); - return; - } + cc = tcg_cond_to_s390_cond[c]; - /* - * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. - * If the immediate we've been given does not fit that range, we'll - * fall back to separate compare and branch instructions using the - * larger comparison range afforded by COMPARE IMMEDIATE. - */ - if (type == TCG_TYPE_I32) { - if (is_unsigned) { - opc = RIEc_CLIJ; - in_range = (uint32_t)c2 == (uint8_t)c2; - } else { - opc = RIEc_CIJ; - in_range = (int32_t)c2 == (int8_t)c2; + if (!c2const) { + opc = (type == TCG_TYPE_I32 + ? (is_unsigned ? RIEb_CLRJ : RIEb_CRJ) + : (is_unsigned ? RIEb_CLGRJ : RIEb_CGRJ)); + tgen_compare_branch(s, opc, cc, r1, c2, l); + return; } - } else { - if (is_unsigned) { - opc = RIEc_CLGIJ; - in_range = (uint64_t)c2 == (uint8_t)c2; + + /* + * COMPARE IMMEDIATE AND BRANCH RELATIVE has an 8-bit immediate field. + * If the immediate we've been given does not fit that range, we'll + * fall back to separate compare and branch instructions using the + * larger comparison range afforded by COMPARE IMMEDIATE. + */ + if (type == TCG_TYPE_I32) { + if (is_unsigned) { + opc = RIEc_CLIJ; + in_range = (uint32_t)c2 == (uint8_t)c2; + } else { + opc = RIEc_CIJ; + in_range = (int32_t)c2 == (int8_t)c2; + } } else { - opc = RIEc_CGIJ; - in_range = (int64_t)c2 == (int8_t)c2; + if (is_unsigned) { + opc = RIEc_CLGIJ; + in_range = (uint64_t)c2 == (uint8_t)c2; + } else { + opc = RIEc_CGIJ; + in_range = (int64_t)c2 == (int8_t)c2; + } + } + if (in_range) { + tgen_compare_imm_branch(s, opc, cc, r1, c2, l); + return; } - } - if (in_range) { - tgen_compare_imm_branch(s, opc, cc, r1, c2, l); - return; } cc = tgen_cmp(s, type, c, r1, c2, c2const, false); @@ -1834,11 +1884,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->oi = oi; ldst->addrlo_reg = addr_reg; - /* We are expecting a_bits to max out at 7, much lower than TMLL. */ tcg_debug_assert(a_mask <= 0xffff); tcg_out_insn(s, RI, TMLL, addr_reg, a_mask); - tcg_out16(s, RI_BRC | (7 << 4)); /* CC in {1,2,3} */ + tcg_out16(s, RI_BRC | (S390_TM_NE << 4)); ldst->label_ptr[0] = s->code_ptr++; } @@ -1919,7 +1968,7 @@ static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, l2 = gen_new_label(); tcg_out_insn(s, RI, TMLL, addr_reg, 15); - tgen_branch(s, 7, l1); /* CC in {1,2,3} */ + tgen_branch(s, S390_TM_NE, l1); } tcg_debug_assert(!need_bswap);