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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id ij23-20020a170902ab5700b001c582de968dsm10038433plb.72.2023.10.25.17.16.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 17:16:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/29] tcg/loongarch64: Support TCG_COND_TST{EQ,NE} Date: Wed, 25 Oct 2023 17:14:07 -0700 Message-Id: <20231026001542.1141412-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231026001542.1141412-1-richard.henderson@linaro.org> References: <20231026001542.1141412-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 56 ++++++++++++++++++++++---------- 1 file changed, 38 insertions(+), 18 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index ccf133db4b..4e850a29e5 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -555,6 +555,7 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, case TCG_COND_GEU: /* -> LTU */ case TCG_COND_GT: /* -> LE */ case TCG_COND_GTU: /* -> LEU */ + case TCG_COND_TSTEQ: /* -> TSTNE */ cond = tcg_invert_cond(cond); flags ^= SETCOND_INV; break; @@ -611,6 +612,18 @@ static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, } break; + case TCG_COND_TSTNE: + flags |= SETCOND_NEZ; + if (!c2) { + tcg_out_opc_and(s, ret, arg1, arg2); + } else if (arg2 >= 0 && arg2 <= 0xfff) { + tcg_out_opc_andi(s, ret, arg1, arg2); + } else { + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); + tcg_out_opc_and(s, ret, arg1, TCG_REG_TMP0); + } + break; + case TCG_COND_LT: case TCG_COND_LTU: if (c2) { @@ -695,29 +708,36 @@ static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, * Branch helpers */ -static const struct { - LoongArchInsn op; - bool swap; -} tcg_brcond_to_loongarch[] = { - [TCG_COND_EQ] = { OPC_BEQ, false }, - [TCG_COND_NE] = { OPC_BNE, false }, - [TCG_COND_LT] = { OPC_BGT, true }, - [TCG_COND_GE] = { OPC_BLE, true }, - [TCG_COND_LE] = { OPC_BLE, false }, - [TCG_COND_GT] = { OPC_BGT, false }, - [TCG_COND_LTU] = { OPC_BGTU, true }, - [TCG_COND_GEU] = { OPC_BLEU, true }, - [TCG_COND_LEU] = { OPC_BLEU, false }, - [TCG_COND_GTU] = { OPC_BGTU, false } -}; - static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, TCGReg arg2, TCGLabel *l) { - LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; + static const struct { + LoongArchInsn op; + bool swap; + } tcg_brcond_to_loongarch[16] = { + [TCG_COND_EQ] = { OPC_BEQ, false }, + [TCG_COND_NE] = { OPC_BNE, false }, + [TCG_COND_LT] = { OPC_BGT, true }, + [TCG_COND_GE] = { OPC_BLE, true }, + [TCG_COND_LE] = { OPC_BLE, false }, + [TCG_COND_GT] = { OPC_BGT, false }, + [TCG_COND_LTU] = { OPC_BGTU, true }, + [TCG_COND_GEU] = { OPC_BLEU, true }, + [TCG_COND_LEU] = { OPC_BLEU, false }, + [TCG_COND_GTU] = { OPC_BGTU, false } + }; + LoongArchInsn op; + + if (is_tst_cond(cond)) { + tcg_out_opc_and(s, TCG_REG_TMP0, arg1, arg2); + arg1 = TCG_REG_TMP0; + arg2 = TCG_REG_ZERO; + cond = tcg_tst_eqne_cond(cond); + } + + op = tcg_brcond_to_loongarch[cond].op tcg_debug_assert(op != 0); - if (tcg_brcond_to_loongarch[cond].swap) { TCGReg t = arg1; arg1 = arg2;