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[176.172.55.165]) by smtp.gmail.com with ESMTPSA id 17-20020a170906019100b009ad8d444be4sm8463539ejb.43.2023.10.24.09.59.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 24 Oct 2023 09:59:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , =?utf-8?q?Philippe_Mat?= =?utf-8?q?hieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PATCH v2 4/9] target/mips: Use tcg_gen_extract_i32 Date: Tue, 24 Oct 2023 18:58:57 +0200 Message-ID: <20231024165903.40861-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231024165903.40861-1-philmd@linaro.org> References: <20231024165903.40861-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62f; envelope-from=philmd@linaro.org; helo=mail-ej1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Inspired-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/tcg/translate.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 13e43fa3b6..2586d9c85a 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1269,8 +1269,7 @@ static inline void gen_load_srsgpr(int from, int to) TCGv_ptr addr = tcg_temp_new_ptr(); tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); - tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); - tcg_gen_andi_i32(t2, t2, 0xf); + tcg_gen_extract_i32(t2, t2, CP0SRSCtl_PSS, 4); tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); tcg_gen_ext_i32_ptr(addr, t2); tcg_gen_add_ptr(addr, tcg_env, addr); @@ -1289,8 +1288,7 @@ static inline void gen_store_srsgpr(int from, int to) gen_load_gpr(t0, from); tcg_gen_ld_i32(t2, tcg_env, offsetof(CPUMIPSState, CP0_SRSCtl)); - tcg_gen_shri_i32(t2, t2, CP0SRSCtl_PSS); - tcg_gen_andi_i32(t2, t2, 0xf); + tcg_gen_extract_i32(t2, t2, CP0SRSCtl_PSS, 4); tcg_gen_muli_i32(t2, t2, sizeof(target_ulong) * 32); tcg_gen_ext_i32_ptr(addr, t2); tcg_gen_add_ptr(addr, tcg_env, addr); @@ -8981,13 +8979,11 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_extu_i32_tl(bcond, t0); goto likely; case OPC_BC1T: - tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); - tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extract_i32(t0, fpu_fcr31, get_fp_bit(cc), 1); tcg_gen_extu_i32_tl(bcond, t0); goto not_likely; case OPC_BC1TL: - tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); - tcg_gen_andi_i32(t0, t0, 1); + tcg_gen_extract_i32(t0, fpu_fcr31, get_fp_bit(cc), 1); tcg_gen_extu_i32_tl(bcond, t0); likely: ctx->hflags |= MIPS_HFLAG_BL;