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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id k26-20020a63ba1a000000b005b25a04cf8bsm4023772pgf.12.2023.10.22.16.29.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Oct 2023 16:29:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v5 25/94] target/sparc: Move RDTBR, FLUSHW to decodetree Date: Sun, 22 Oct 2023 16:28:23 -0700 Message-Id: <20231022232932.80507-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022232932.80507-1-richard.henderson@linaro.org> References: <20231022232932.80507-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Tested-by: Mark Cave-Ayland Acked-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++++ target/sparc/translate.c | 23 +++++++++++------------ 2 files changed, 16 insertions(+), 12 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 7d91a7bc83..0b6f4c9c38 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -76,6 +76,11 @@ RDPR_gl 10 rd:5 101010 10000 0 0000000000000 RDPR_strand_status 10 rd:5 101010 11010 0 0000000000000 RDPR_ver 10 rd:5 101010 11111 0 0000000000000 +{ + FLUSHW 10 00000 101011 00000 0 0000000000000 + RDTBR 10 rd:5 101011 00000 0 0000000000000 +} + Tcc_r 10 0 cond:4 111010 rs1:5 0 cc:1 0000000 rs2:5 { # For v7, the entire simm13 field is present, but masked to 7 bits. diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 6e415d7070..67d3292e68 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -39,6 +39,7 @@ #ifdef TARGET_SPARC64 # define gen_helper_rdpsr(D, E) qemu_build_not_reached() #else +# define gen_helper_flushw(E) qemu_build_not_reached() # define gen_helper_rdccr(D, E) qemu_build_not_reached() # define gen_helper_rdcwp(D, E) qemu_build_not_reached() # define gen_helper_tick_get_count(D, E, T, C) qemu_build_not_reached() @@ -3464,6 +3465,7 @@ static TCGv do_rdtba(DisasContext *dc, TCGv dst) return cpu_tbr; } +TRANS(RDTBR, 32, do_rd_special, supervisor(dc), a->rd, do_rdtba) TRANS(RDPR_tba, 64, do_rd_special, supervisor(dc), a->rd, do_rdtba) static TCGv do_rdpstate(DisasContext *dc, TCGv dst) @@ -3562,6 +3564,15 @@ static TCGv do_rdver(DisasContext *dc, TCGv dst) TRANS(RDPR_ver, 64, do_rd_special, supervisor(dc), a->rd, do_rdver) +static bool trans_FLUSHW(DisasContext *dc, arg_FLUSHW *a) +{ + if (avail_64(dc)) { + gen_helper_flushw(tcg_env); + return advance_pc(dc); + } + return false; +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -3592,18 +3603,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) TCGv cpu_dst __attribute__((unused)) = tcg_temp_new(); TCGv cpu_tmp0 __attribute__((unused)); -#if defined(TARGET_SPARC64) || !defined(CONFIG_USER_ONLY) - if (xop == 0x2b) { /* rdtbr / V9 flushw */ -#ifdef TARGET_SPARC64 - gen_helper_flushw(tcg_env); -#else - if (!supervisor(dc)) - goto priv_insn; - gen_store_gpr(dc, rd, cpu_tbr); -#endif - break; - } -#endif if (xop == 0x34) { /* FPU Operations */ if (gen_trap_ifnofpu(dc)) { goto jmp_insn;