@@ -241,10 +241,13 @@ RETRY 10 00001 111110 00000 0 0000000000000
FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2
FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2
+FMOVq 10 ..... 110100 00000 0 0000 0011 ..... @r_r2
FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2
FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2
+FNEGq 10 ..... 110100 00000 0 0000 0111 ..... @r_r2
FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
+FABSq 10 ..... 110100 00000 0 0000 1011 ..... @r_r2
FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2
FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2
FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2
@@ -59,6 +59,8 @@
#define gen_helper_fxtod ({ qemu_build_not_reached(); NULL; })
#define gen_helper_fxtos ({ qemu_build_not_reached(); NULL; })
#define gen_helper_fxtoq ({ qemu_build_not_reached(); NULL; })
+#define gen_helper_fabsq ({ qemu_build_not_reached(); NULL; })
+#define gen_helper_fnegq ({ qemu_build_not_reached(); NULL; })
#define gen_helper_fnegd(D, S) qemu_build_not_reached()
#define gen_helper_fabsd(D, S) qemu_build_not_reached()
#define gen_helper_done(E) qemu_build_not_reached()
@@ -271,18 +273,6 @@ static void gen_op_store_QT0_fpr(unsigned int dst)
offsetof(CPU_QuadU, ll.lower));
}
-#ifdef TARGET_SPARC64
-static void gen_move_Q(DisasContext *dc, unsigned int rd, unsigned int rs)
-{
- rd = QFPREG(rd);
- rs = QFPREG(rs);
-
- tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
- tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
- gen_update_fprs_dirty(dc, rd);
-}
-#endif
-
/* moves */
#ifdef CONFIG_USER_ONLY
#define supervisor(dc) 0
@@ -1657,19 +1647,6 @@ static int gen_trap_ifnofpu(DisasContext *dc)
return 0;
}
-#ifdef TARGET_SPARC64
-static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs,
- void (*gen)(TCGv_ptr))
-{
- gen_op_load_fpr_QT1(QFPREG(rs));
-
- gen(tcg_env);
-
- gen_op_store_QT0_fpr(QFPREG(rd));
- gen_update_fprs_dirty(dc, QFPREG(rd));
-}
-#endif
-
/* asi moves */
typedef enum {
GET_ASI_HELPER,
@@ -4870,6 +4847,50 @@ TRANS(FiTOd, ALL, do_env_df, a, gen_helper_fitod)
TRANS(FsTOd, ALL, do_env_df, a, gen_helper_fstod)
TRANS(FsTOx, 64, do_env_df, a, gen_helper_fstox)
+static bool trans_FMOVq(DisasContext *dc, arg_FMOVq *a)
+{
+ int rd, rs;
+
+ if (!avail_64(dc)) {
+ return false;
+ }
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ rd = QFPREG(a->rd);
+ rs = QFPREG(a->rs);
+ tcg_gen_mov_i64(cpu_fpr[rd / 2], cpu_fpr[rs / 2]);
+ tcg_gen_mov_i64(cpu_fpr[rd / 2 + 1], cpu_fpr[rs / 2 + 1]);
+ gen_update_fprs_dirty(dc, rd);
+ return advance_pc(dc);
+}
+
+static bool do_qq(DisasContext *dc, arg_r_r *a,
+ void (*func)(TCGv_env))
+{
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+ if (gen_trap_float128(dc)) {
+ return true;
+ }
+
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_op_load_fpr_QT1(QFPREG(a->rs));
+ func(tcg_env);
+ gen_op_store_QT0_fpr(QFPREG(a->rd));
+ gen_update_fprs_dirty(dc, QFPREG(a->rd));
+ return advance_pc(dc);
+}
+
+TRANS(FNEGq, 64, do_qq, a, gen_helper_fnegq)
+TRANS(FABSq, 64, do_qq, a, gen_helper_fabsq)
+
static bool do_env_qq(DisasContext *dc, arg_r_r *a,
void (*func)(TCGv_env))
{
@@ -5224,74 +5245,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
TCGv cpu_dst __attribute__((unused)) = tcg_temp_new();
if (xop == 0x34) { /* FPU Operations */
- if (gen_trap_ifnofpu(dc)) {
- goto jmp_insn;
- }
- gen_op_clear_ieee_excp_and_FTT();
- rs1 = GET_FIELD(insn, 13, 17);
- rs2 = GET_FIELD(insn, 27, 31);
- xop = GET_FIELD(insn, 18, 26);
-
- switch (xop) {
- case 0x1: /* fmovs */
- case 0x5: /* fnegs */
- case 0x9: /* fabss */
- case 0x2: /* V9 fmovd */
- case 0x6: /* V9 fnegd */
- case 0xa: /* V9 fabsd */
- case 0x29: /* fsqrts */
- case 0xc4: /* fitos */
- case 0xd1: /* fstoi */
- case 0x2a: /* fsqrtd */
- case 0x82: /* V9 fdtox */
- case 0x88: /* V9 fxtod */
- case 0x2b: /* fsqrtq */
- case 0x41: /* fadds */
- case 0x45: /* fsubs */
- case 0x49: /* fmuls */
- case 0x4d: /* fdivs */
- case 0x42: /* faddd */
- case 0x46: /* fsubd */
- case 0x4a: /* fmuld */
- case 0x4e: /* fdivd */
- case 0x43: /* faddq */
- case 0x47: /* fsubq */
- case 0x4b: /* fmulq */
- case 0x4f: /* fdivq */
- case 0x69: /* fsmuld */
- case 0x6e: /* fdmulq */
- case 0xc6: /* fdtos */
- case 0xd2: /* fdtoi */
- case 0x84: /* V9 fxtos */
- case 0xc8: /* fitod */
- case 0xc9: /* fstod */
- case 0x81: /* V9 fstox */
- case 0xc7: /* fqtos */
- case 0xd3: /* fqtoi */
- case 0xcb: /* fqtod */
- case 0x83: /* V9 fqtox */
- case 0xcc: /* fitoq */
- case 0xcd: /* fstoq */
- case 0xce: /* fdtoq */
- case 0x8c: /* V9 fxtoq */
- g_assert_not_reached(); /* in decodetree */
-#ifdef TARGET_SPARC64
- case 0x3: /* V9 fmovq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_move_Q(dc, rd, rs2);
- break;
- case 0x7: /* V9 fnegq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
- break;
- case 0xb: /* V9 fabsq */
- CHECK_FPU_FEATURE(dc, FLOAT128);
- gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
- break;
-#endif
- default:
- goto illegal_insn;
- }
+ goto illegal_insn; /* in decodetree */
} else if (xop == 0x35) { /* FPU Operations */
#ifdef TARGET_SPARC64
int cond;
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/insns.decode | 3 + target/sparc/translate.c | 140 +++++++++++++------------------------- 2 files changed, 50 insertions(+), 93 deletions(-)