@@ -239,8 +239,11 @@ DONE 10 00000 111110 00000 0 0000000000000
RETRY 10 00001 111110 00000 0 0000000000000
FMOVs 10 ..... 110100 00000 0 0000 0001 ..... @r_r2
+FMOVd 10 ..... 110100 00000 0 0000 0010 ..... @r_r2
FNEGs 10 ..... 110100 00000 0 0000 0101 ..... @r_r2
+FNEGd 10 ..... 110100 00000 0 0000 0110 ..... @r_r2
FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
+FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2
{
[
@@ -266,9 +269,13 @@ FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2
BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r
+ FSRCd 10 ..... 110110 ..... 0 0111 0100 00000 @r_r1 # FSRC1d
FSRCs 10 ..... 110110 ..... 0 0111 0101 00000 @r_r1 # FSRC1s
+ FSRCd 10 ..... 110110 00000 0 0111 1000 ..... @r_r2 # FSRC2d
FSRCs 10 ..... 110110 00000 0 0111 1001 ..... @r_r2 # FSRC2s
+ FNOTd 10 ..... 110110 ..... 0 0110 1010 00000 @r_r1 # FNOT1d
FNOTs 10 ..... 110110 ..... 0 0110 1011 00000 @r_r1 # FNOT1s
+ FNOTd 10 ..... 110110 00000 0 0110 0110 ..... @r_r2 # FNOT2d
FNOTs 10 ..... 110110 00000 0 0110 0111 ..... @r_r2 # FNOT2s
]
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
@@ -54,6 +54,8 @@
#define gen_helper_write_softint(E, S) qemu_build_not_reached()
#define gen_helper_saved ({ qemu_build_not_reached(); NULL; })
#define gen_helper_restored ({ qemu_build_not_reached(); NULL; })
+#define gen_helper_fnegd(D, S) qemu_build_not_reached()
+#define gen_helper_fabsd(D, S) qemu_build_not_reached()
#define gen_helper_done(E) qemu_build_not_reached()
#define gen_helper_retry(E) qemu_build_not_reached()
#define gen_helper_udivx(D, E, A, B) qemu_build_not_reached()
@@ -1416,6 +1418,24 @@ static void gen_op_fabss(TCGv_i32 dst, TCGv_i32 src)
gen_helper_fabss(dst, src);
}
+static void gen_op_fmovd(TCGv_i64 dst, TCGv_i64 src)
+{
+ gen_op_clear_ieee_excp_and_FTT();
+ tcg_gen_mov_i64(dst, src);
+}
+
+static void gen_op_fnegd(TCGv_i64 dst, TCGv_i64 src)
+{
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_helper_fnegd(dst, src);
+}
+
+static void gen_op_fabsd(TCGv_i64 dst, TCGv_i64 src)
+{
+ gen_op_clear_ieee_excp_and_FTT();
+ gen_helper_fabsd(dst, src);
+}
+
#ifdef TARGET_SPARC64
static void gen_op_fcmps(int fccno, TCGv_i32 r_rs1, TCGv_i32 r_rs2)
{
@@ -1635,21 +1655,6 @@ static void gen_fop_DD(DisasContext *dc, int rd, int rs,
gen_store_fpr_D(dc, rd, dst);
}
-#ifdef TARGET_SPARC64
-static void gen_ne_fop_DD(DisasContext *dc, int rd, int rs,
- void (*gen)(TCGv_i64, TCGv_i64))
-{
- TCGv_i64 dst, src;
-
- src = gen_load_fpr_D(dc, rs);
- dst = gen_dest_fpr_D(dc, rd);
-
- gen(dst, src);
-
- gen_store_fpr_D(dc, rd, dst);
-}
-#endif
-
static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2,
void (*gen)(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64))
{
@@ -4989,6 +4994,28 @@ TRANS(FABSs, ALL, do_ff, a, gen_op_fabss)
TRANS(FSRCs, VIS1, do_ff, a, tcg_gen_mov_i32)
TRANS(FNOTs, VIS1, do_ff, a, tcg_gen_not_i32)
+static bool do_dd(DisasContext *dc, arg_r_r *a,
+ void (*func)(TCGv_i64, TCGv_i64))
+{
+ TCGv_i64 dst, src;
+
+ if (gen_trap_ifnofpu(dc)) {
+ return true;
+ }
+
+ dst = gen_dest_fpr_D(dc, a->rd);
+ src = gen_load_fpr_D(dc, a->rs);
+ func(dst, src);
+ gen_store_fpr_D(dc, a->rd, dst);
+ return advance_pc(dc);
+}
+
+TRANS(FMOVd, 64, do_dd, a, gen_op_fmovd)
+TRANS(FNEGd, 64, do_dd, a, gen_op_fnegd)
+TRANS(FABSd, 64, do_dd, a, gen_op_fabsd)
+TRANS(FSRCd, VIS1, do_dd, a, tcg_gen_mov_i64)
+TRANS(FNOTd, VIS1, do_dd, a, tcg_gen_not_i64)
+
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -5032,6 +5059,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x1: /* fmovs */
case 0x5: /* fnegs */
case 0x9: /* fabss */
+ case 0x2: /* V9 fmovd */
+ case 0x6: /* V9 fnegd */
+ case 0xa: /* V9 fabsd */
g_assert_not_reached(); /* in decodetree */
case 0x29: /* fsqrts */
gen_fop_FF(dc, rd, rs2, gen_helper_fsqrts);
@@ -5134,24 +5164,14 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
gen_fop_FQ(dc, rd, rs2, gen_helper_fqtoi);
break;
#ifdef TARGET_SPARC64
- case 0x2: /* V9 fmovd */
- cpu_src1_64 = gen_load_fpr_D(dc, rs2);
- gen_store_fpr_D(dc, rd, cpu_src1_64);
- break;
case 0x3: /* V9 fmovq */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_move_Q(dc, rd, rs2);
break;
- case 0x6: /* V9 fnegd */
- gen_ne_fop_DD(dc, rd, rs2, gen_helper_fnegd);
- break;
case 0x7: /* V9 fnegq */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fnegq);
break;
- case 0xa: /* V9 fabsd */
- gen_ne_fop_DD(dc, rd, rs2, gen_helper_fabsd);
- break;
case 0xb: /* V9 fabsq */
CHECK_FPU_FEATURE(dc, FLOAT128);
gen_ne_fop_QQ(dc, rd, rs2, gen_helper_fabsq);
@@ -5364,6 +5384,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
case 0x06b: /* VIS I fnot1s */
case 0x075: /* VIS I fsrc1s */
case 0x079: /* VIS I fsrc2s */
+ case 0x066: /* VIS I fnot2 */
+ case 0x06a: /* VIS I fnot1 */
+ case 0x074: /* VIS I fsrc1 */
+ case 0x078: /* VIS I fsrc2 */
g_assert_not_reached(); /* in decodetree */
case 0x020: /* VIS I fcmple16 */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -5547,10 +5571,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_andc_i32);
break;
- case 0x066: /* VIS I fnot2 */
- CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DD(dc, rd, rs2, tcg_gen_not_i64);
- break;
case 0x068: /* VIS I fandnot1 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_andc_i64);
@@ -5559,10 +5579,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs2, rs1, tcg_gen_andc_i32);
break;
- case 0x06a: /* VIS I fnot1 */
- CHECK_FPU_FEATURE(dc, VIS1);
- gen_ne_fop_DD(dc, rd, rs1, tcg_gen_not_i64);
- break;
case 0x06c: /* VIS I fxor */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs1, rs2, tcg_gen_xor_i64);
@@ -5595,10 +5611,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_eqv_i32);
break;
- case 0x074: /* VIS I fsrc1 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs1);
- gen_store_fpr_D(dc, rd, cpu_src1_64);
break;
case 0x076: /* VIS I fornot2 */
CHECK_FPU_FEATURE(dc, VIS1);
@@ -5608,11 +5620,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_FFF(dc, rd, rs1, rs2, tcg_gen_orc_i32);
break;
- case 0x078: /* VIS I fsrc2 */
- CHECK_FPU_FEATURE(dc, VIS1);
- cpu_src1_64 = gen_load_fpr_D(dc, rs2);
- gen_store_fpr_D(dc, rd, cpu_src1_64);
- break;
case 0x07a: /* VIS I fornot1 */
CHECK_FPU_FEATURE(dc, VIS1);
gen_ne_fop_DDD(dc, rd, rs2, rs1, tcg_gen_orc_i64);
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/insns.decode | 7 +++ target/sparc/translate.c | 91 +++++++++++++++++++++------------------ 2 files changed, 56 insertions(+), 42 deletions(-)