diff mbox series

[v4,05/90] configs: Enable MTTCG for sparc, sparc64

Message ID	20231022060031.490251-6-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v4 05/90] configs: Enable MTTCG for sparc, sparc64 Date: Sat, 21 Oct 2023 22:59:06 -0700 Message-Id: <20231022060031.490251-6-richard.henderson@linaro.org> In-Reply-To: <20231022060031.490251-1-richard.henderson@linaro.org> References: <20231022060031.490251-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/sparc: Convert to decodetree \| expand [v4,00/90] target/sparc: Convert to decodetree [v4,01/90] target/sparc: Clear may_lookup for npc == DYNAMIC_PC [v4,02/90] target/sparc: Implement check_align inline [v4,03/90] target/sparc: Avoid helper_raise_exception in helper_st_asi [v4,04/90] target/sparc: Set TCG_GUEST_DEFAULT_MO [v4,05/90] configs: Enable MTTCG for sparc, sparc64 [v4,06/90] target/sparc: Define features via cpu-feature.h.inc [v4,07/90] target/sparc: Use CPU_FEATURE_BIT_* for cpu properties [v4,08/90] target/sparc: Remove sparcv7 cpu features [v4,09/90] target/sparc: Add decodetree infrastructure [v4,10/90] target/sparc: Define AM_CHECK for sparc32 [v4,11/90] target/sparc: Move CALL to decodetree [v4,12/90] target/sparc: Move BPcc and Bicc to decodetree [v4,13/90] target/sparc: Move BPr to decodetree [v4,14/90] target/sparc: Move FBPfcc and FBfcc to decodetree [v4,15/90] target/sparc: Merge gen_cond with only caller [v4,16/90] target/sparc: Merge gen_fcond with only caller [v4,17/90] target/sparc: Merge gen_branch_[an] with only caller [v4,18/90] target/sparc: Pass DisasCompare to advance_jump_cond [v4,19/90] target/sparc: Move SETHI to decodetree [v4,20/90] target/sparc: Move Tcc to decodetree [v4,21/90] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree [v4,22/90] target/sparc: Move RDPSR, RDHPR to decodetree [v4,23/90] target/sparc: Move RDWIM, RDPR to decodetree [v4,24/90] target/sparc: Move RDTBR, FLUSHW to decodetree [v4,25/90] target/sparc: Move WRASR to decodetree [v4,26/90] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree [v4,27/90] target/sparc: Move WRWIM, WRPR to decodetree [v4,28/90] target/sparc: Move WRTBR, WRHPR to decodetree [v4,29/90] target/sparc: Move basic arithmetic to decodetree [v4,30/90] target/sparc: Move ADDC to decodetree [v4,31/90] target/sparc: Move MULX to decodetree [v4,32/90] target/sparc: Move UMUL, SMUL to decodetree [v4,33/90] target/sparc: Move SUBC to decodetree [v4,34/90] target/sparc: Move UDIVX, SDIVX to decodetree [v4,35/90] target/sparc: Move UDIV, SDIV to decodetree [v4,36/90] target/sparc: Move TADD, TSUB, MULS to decodetree [v4,37/90] target/sparc: Move SLL, SRL, SRA to decodetree [v4,38/90] target/sparc: Move MOVcc, MOVR to decodetree [v4,39/90] target/sparc: Move POPC to decodetree [v4,40/90] target/sparc: Convert remaining v8 coproc insns to decodetree [v4,41/90] target/sparc: Move JMPL, RETT, RETURN to decodetree [v4,42/90] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree [v4,43/90] target/sparc: Move DONE, RETRY to decodetree [v4,44/90] target/sparc: Split out resolve_asi [v4,45/90] target/sparc: Drop ifdef around get_asi and friends [v4,46/90] target/sparc: Split out ldst functions with asi pre-computed [v4,47/90] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX [v4,48/90] target/sparc: Move simple integer load/store to decodetree [v4,49/90] target/sparc: Move asi integer load/store to decodetree [v4,50/90] target/sparc: Move LDSTUB, LDSTUBA to decodetree [v4,51/90] target/sparc: Move SWAP, SWAPA to decodetree [v4,52/90] target/sparc: Move CASA, CASXA to decodetree [v4,53/90] target/sparc: Move PREFETCH, PREFETCHA to decodetree [v4,54/90] target/sparc: Split out fp ldst functions with asi precomputed [v4,55/90] target/sparc: Move simple fp load/store to decodetree [v4,56/90] target/sparc: Move asi fp load/store to decodetree [v4,57/90] target/sparc: Move LDFSR, STFSR to decodetree [v4,58/90] target/sparc: Merge LDFSR, LDXFSR implementations [v4,59/90] target/sparc: Move EDGE* to decodetree [v4,60/90] target/sparc: Move ARRAY* to decodetree [v4,61/90] target/sparc: Move ADDRALIGN* to decodetree [v4,62/90] target/sparc: Move BMASK to decodetree [v4,63/90] target/sparc: Move FMOVS, FNEGS, FABSS, FSRCS, FNOTS to decodetree [v4,64/90] target/sparc: Move FMOVD, FNEGD, FABSD, FSRCD, FNOTD to decodetree [v4,65/90] target/sparc: Use tcg_gen_vec_{add,sub}* [v4,66/90] target/sparc: Move gen_ne_fop_FFF insns to decodetree [v4,67/90] target/sparc: Move gen_ne_fop_DDD insns to decodetree [v4,68/90] target/sparc: Move PDIST to decodetree [v4,69/90] target/sparc: Move gen_gsr_fop_DDD insns to decodetree [v4,70/90] target/sparc: Move gen_fop_FF insns to decodetree [v4,71/90] target/sparc: Move gen_fop_DD insns to decodetree [v4,72/90] target/sparc: Move FSQRTq to decodetree [v4,73/90] target/sparc: Move gen_fop_FFF insns to decodetree [v4,74/90] target/sparc: Move gen_fop_DDD insns to decodetree [v4,75/90] target/sparc: Move gen_fop_QQQ insns to decodetree [v4,76/90] target/sparc: Move FSMULD to decodetree [v4,77/90] target/sparc: Move FDMULQ to decodetree [v4,78/90] target/sparc: Move gen_fop_FD insns to decodetree [v4,79/90] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree [v4,80/90] target/sparc: Move FqTOs, FqTOi to decodetree [v4,81/90] target/sparc: Move FqTOd, FqTOx to decodetree [v4,82/90] target/sparc: Move FiTOq, FsTOq to decodetree [v4,83/90] target/sparc: Move FdTOq, FxTOq to decodetree [v4,84/90] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree [v4,85/90] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree [v4,86/90] target/sparc: Convert FCMP, FCMPE to decodetree [v4,87/90] target/sparc: Move FPCMP* to decodetree [v4,88/90] target/sparc: Move FPACK16, FPACKFIX to decodetree [v4,89/90] target/sparc: Convert FZERO, FONE to decodetree [v4,90/90] target/sparc: Remove disas_sparc_legacy

Commit Message

Richard Henderson Oct. 22, 2023, 5:59 a.m. UTC

This will be of small comfort to sparc64, because both
sun4u and sun4v board models force max_cpus = 1.
But it does enable actual smp for sparc32 sun4m.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configs/targets/sparc-softmmu.mak   | 1 +
 configs/targets/sparc64-softmmu.mak | 1 +
 2 files changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index 454eb35499..a5d9200382 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,2 +1,3 @@ 
 TARGET_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index d3f8a3b710..36ca64ec41 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -1,3 +1,4 @@ 
 TARGET_ARCH=sparc64
 TARGET_BASE_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y