From patchwork Sun Oct 22 05:59:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 736940 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp1003966wrl; Sat, 21 Oct 2023 23:05:01 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHnvhptSAPwOso7mFHsOEHdSFpRAQ/qk5W0KvIS1DkOpKaz5PtP/qYy241bYjZAYYjRy/cl X-Received: by 2002:a05:620a:2412:b0:779:cf30:600b with SMTP id d18-20020a05620a241200b00779cf30600bmr1836887qkn.4.1697954701637; Sat, 21 Oct 2023 23:05:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697954701; cv=none; d=google.com; s=arc-20160816; b=V49flATKR7p92znjY4ueRnIAdmRE267IAPtMDOQLhdwhI6GV76R6PWuotq7VFRiKiy tK6VAb6jkgF0q4pRcPmiBtIc6kRSP9ADxZpULbjF2/aHyy2W4omvWQU05J1L0xgiB77Y Bn20/VDcKAERQeEqKvRzFuPCjBEpPMf80H1Qi9rzXs8FfO0MTgxNsWp5iz3Xbxm7CGIi q/ctjsw8fV2LYhM9pg4UEkKnIOKmI1cifcZNugJ75d+8FYc5os0d4MGCn29bwJytnLR+ t2L2PdfUCWuaM2ooyd1g/RALj5WCRMp3kXy43CsVfIc9BTIRnJctJ1ddjk6CUF8kchdb Gfrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Fqur4Bi6E3LW+knuatXkBdwIHpDBdwugkOArA2uSeic=; fh=TYrED6TOMxGX0VC4GtjviASLbYyJe19+7/tKWjN44KQ=; b=Rm4CelLkCOZ7d8F9y1wjUr6e7CTUoU9B0lbcJeTK+yrn6FeOX2yXUJQeNwCFohPDVf MA+pSbaf5SS3fP51OwCXg7AnNFklQ0320c5dRzRkic7AnaQC0Xg4O06UvABz/lyjPW9j ccTzJlowyb3dX1I7+fZcJK6lgA43X/KUHrIa0ODSyJcKo2OIs61ooTv7PkSe476JqM56 o9xvL0uaBxOFLD2tH1w2rvXS4q8ELGdos41O1n47OFiMnLZQ878RVb5Inlslb1qrSjz2 aX2gQhUZjsvbJ795G4eiQ5p4UNq5t00GgFAohTK9ElDy8YEuMOIdujP1SHV7Q15grzII s+ZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PSBN35+P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e8-20020a05620a208800b007775a24742asi3749375qka.613.2023.10.21.23.05.01 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 21 Oct 2023 23:05:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PSBN35+P; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1quRZu-00008M-6x; Sun, 22 Oct 2023 02:04:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1quRZr-0008Td-VG for qemu-devel@nongnu.org; Sun, 22 Oct 2023 02:04:43 -0400 Received: from mail-oo1-xc2a.google.com ([2607:f8b0:4864:20::c2a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1quRZp-0002Dc-C5 for qemu-devel@nongnu.org; Sun, 22 Oct 2023 02:04:43 -0400 Received: by mail-oo1-xc2a.google.com with SMTP id 006d021491bc7-581fb6f53fcso1396051eaf.2 for ; Sat, 21 Oct 2023 23:04:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697954680; x=1698559480; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Fqur4Bi6E3LW+knuatXkBdwIHpDBdwugkOArA2uSeic=; b=PSBN35+POUQdv7xh6KNZpmqcsGSspLYzoWM/nbm8cb4dTwg6vJzG/shPyX4MQFd2uZ 3T8yHtwTriaLRZvHGLeK43edu5Hk4CB2hYQqrN9Poo2mL7rKKvbeObL8uWQctFPpZ1CX 9BWhMO+MsRYYq88Jb5Zi6tSVCKo9wNSgv6gTT8+Bi3cAmBbMw5tu2sIrh3dq1v7VVyha urQC0fIvdXT1+5xdViq7p7n3f3SwS6I4Xo2dTHgnA13SrzW6ofGTzgWtCYaAkcVOiAvE j4+gyClhRT+w+bfew81EcOyWG1HexGqL/kj7NwP5NwdxP03nQuADCnXxlXW2Dv3QFYoM aiqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697954680; x=1698559480; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Fqur4Bi6E3LW+knuatXkBdwIHpDBdwugkOArA2uSeic=; b=VQnBMFywyCRl+AtOprjQPEYUFbK1HuK+G4F6o24BJ40g+VUH952vCbbUpTCImN49KE Pftc0AtbEXK9h/smtyfzcuCsbRYwVhjEMdNE9C0XuyPpVon+6zckA93aepaOHq5S6E0a vNzSqHI/9GH9nIuFt8/5KUkFqQA2w3/Er6S7hPRkDm7nXGPLEXqjVD9WNKvbKzaYFVVP C+kXHCR+4GsFv/xrCAmHvcOBkeMNrJiw1LfWUco5N4b9peozdSOKD5fTDGutvY3OxopW V/Qv3mnjIGrgC4dqB9yUOLY8QoB4muRqn1KXwRgWZz/Q0bRS1+D/ec+ggrXkrmW5KNOE eLVA== X-Gm-Message-State: AOJu0YzPzkmaPM92T1qFyL8QOGdc0YHdGOtOpMtCyLToIO4jLESdnRwd 6AmSQzs5Ew/l55kaCMBOniaH40B79TeSH9a4Yhc= X-Received: by 2002:a05:6358:9387:b0:142:dfc2:a441 with SMTP id h7-20020a056358938700b00142dfc2a441mr8108184rwb.8.1697954680039; Sat, 21 Oct 2023 23:04:40 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id fb13-20020a056a002d8d00b0068a46cd4120sm4007373pfb.199.2023.10.21.23.04.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 21 Oct 2023 23:04:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v4 45/90] target/sparc: Drop ifdef around get_asi and friends Date: Sat, 21 Oct 2023 22:59:46 -0700 Message-Id: <20231022060031.490251-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231022060031.490251-1-richard.henderson@linaro.org> References: <20231022060031.490251-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::c2a; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc2a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mark some of the functions as unused, temporarily. Fix up some tl vs i64 issues revealed in the process. Signed-off-by: Richard Henderson --- target/sparc/translate.c | 187 +++++++++++++++------------------------ 1 file changed, 70 insertions(+), 117 deletions(-) diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9b1bd97947..6802399647 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -58,6 +58,18 @@ #define gen_helper_retry(E) qemu_build_not_reached() #define gen_helper_udivx(D, E, A, B) qemu_build_not_reached() #define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached() +# ifdef CONFIG_USER_ONLY +static void gen_helper_ld_asi(TCGv_i64 r, TCGv_env e, TCGv a, + TCGv_i32 asi, TCGv_i32 mop) +{ + g_assert_not_reached(); +} +static void gen_helper_st_asi(TCGv_env e, TCGv a, TCGv_i64 r, + TCGv_i32 asi, TCGv_i32 mop) +{ + g_assert_not_reached(); +} +# endif #endif /* Dynamic PC, must exit to main loop. */ @@ -1887,7 +1899,6 @@ static void gen_ldstub(DisasContext *dc, TCGv dst, TCGv addr, int mmu_idx) } /* asi moves */ -#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64) typedef enum { GET_ASI_HELPER, GET_ASI_EXCP, @@ -2136,8 +2147,8 @@ static DisasASI get_asi(DisasContext *dc, int insn, MemOp memop) return resolve_asi(dc, asi, memop); } -static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, - int insn, MemOp memop) +static void __attribute__((unused)) +gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn, MemOp memop) { DisasASI da = get_asi(dc, insn, memop); @@ -2171,8 +2182,8 @@ static void gen_ld_asi(DisasContext *dc, TCGv dst, TCGv addr, } } -static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, - int insn, MemOp memop) +static void __attribute__((unused)) +gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, int insn, MemOp memop) { DisasASI da = get_asi(dc, insn, memop); @@ -2247,8 +2258,8 @@ static void gen_st_asi(DisasContext *dc, TCGv src, TCGv addr, } } -static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, - TCGv addr, int insn) +static void __attribute__((unused)) +gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, TCGv addr, int insn) { DisasASI da = get_asi(dc, insn, MO_TEUL); @@ -2265,8 +2276,8 @@ static void gen_swap_asi(DisasContext *dc, TCGv dst, TCGv src, } } -static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, - int insn, int rd) +static void __attribute__((unused)) +gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUL); TCGv oldv; @@ -2287,7 +2298,8 @@ static void gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, } } -static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) +static void __attribute__((unused)) +gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) { DisasASI da = get_asi(dc, insn, MO_UB); @@ -2322,11 +2334,9 @@ static void gen_ldstub_asi(DisasContext *dc, TCGv dst, TCGv addr, int insn) break; } } -#endif -#ifdef TARGET_SPARC64 -static void gen_ldf_asi(DisasContext *dc, TCGv addr, - int insn, int size, int rd) +static void __attribute__((unused)) +gen_ldf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); TCGv_i32 d32; @@ -2434,8 +2444,8 @@ static void gen_ldf_asi(DisasContext *dc, TCGv addr, } } -static void gen_stf_asi(DisasContext *dc, TCGv addr, - int insn, int size, int rd) +static void __attribute__((unused)) +gen_stf_asi(DisasContext *dc, TCGv addr, int insn, int size, int rd) { DisasASI da = get_asi(dc, insn, (size == 4 ? MO_TEUL : MO_TEUQ)); TCGv_i32 d32; @@ -2517,21 +2527,23 @@ static void gen_stf_asi(DisasContext *dc, TCGv addr, } } -static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) +static void __attribute__((unused)) +gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); - TCGv_i64 hi = gen_dest_gpr(dc, rd); - TCGv_i64 lo = gen_dest_gpr(dc, rd + 1); + TCGv hi = gen_dest_gpr(dc, rd); + TCGv lo = gen_dest_gpr(dc, rd + 1); switch (da.type) { case GET_ASI_EXCP: return; case GET_ASI_DTWINX: + assert(TARGET_LONG_BITS == 64); gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_ld_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_ld_i64(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_ld_tl(lo, addr, da.mem_idx, da.memop); break; case GET_ASI_DIRECT: @@ -2545,9 +2557,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) result is byte swapped. Having just performed one 64-bit bswap, we need now to swap the writebacks. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_extr32_i64(lo, hi, tmp); + tcg_gen_extr_i64_tl(lo, hi, tmp); } else { - tcg_gen_extr32_i64(hi, lo, tmp); + tcg_gen_extr_i64_tl(hi, lo, tmp); } } break; @@ -2567,9 +2579,9 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) /* See above. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_extr32_i64(lo, hi, tmp); + tcg_gen_extr_i64_tl(lo, hi, tmp); } else { - tcg_gen_extr32_i64(hi, lo, tmp); + tcg_gen_extr_i64_tl(hi, lo, tmp); } } break; @@ -2579,8 +2591,8 @@ static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) gen_store_gpr(dc, rd + 1, lo); } -static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) +static void __attribute__((unused)) +gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); TCGv lo = gen_load_gpr(dc, rd + 1); @@ -2590,10 +2602,11 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, break; case GET_ASI_DTWINX: + assert(TARGET_LONG_BITS == 64); gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); + tcg_gen_qemu_st_tl(hi, addr, da.mem_idx, da.memop | MO_ALIGN_16); tcg_gen_addi_tl(addr, addr, 8); - tcg_gen_qemu_st_i64(lo, addr, da.mem_idx, da.memop); + tcg_gen_qemu_st_tl(lo, addr, da.mem_idx, da.memop); break; case GET_ASI_DIRECT: @@ -2604,15 +2617,37 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, byte swapped. We will perform one 64-bit LE store, so now we must swap the order of the construction. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_concat32_i64(t64, lo, hi); + tcg_gen_concat_tl_i64(t64, lo, hi); } else { - tcg_gen_concat32_i64(t64, hi, lo); + tcg_gen_concat_tl_i64(t64, hi, lo); } gen_address_mask(dc, addr); tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); } break; + case GET_ASI_BFILL: + assert(TARGET_LONG_BITS == 32); + /* Store 32 bytes of T64 to ADDR. */ + /* ??? The original qemu code suggests 8-byte alignment, dropping + the low bits, but the only place I can see this used is in the + Linux kernel with 32 byte alignment, which would make more sense + as a cacheline-style operation. */ + { + TCGv_i64 t64 = tcg_temp_new_i64(); + TCGv d_addr = tcg_temp_new(); + TCGv eight = tcg_constant_tl(8); + int i; + + tcg_gen_concat_tl_i64(t64, lo, hi); + tcg_gen_andi_tl(d_addr, addr, -8); + for (i = 0; i < 32; i += 8) { + tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); + tcg_gen_add_tl(d_addr, d_addr, eight); + } + } + break; + default: /* ??? In theory we've handled all of the ASIs that are valid for stda, and this should raise DAE_invalid_asi. */ @@ -2623,9 +2658,9 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, /* See above. */ if ((da.memop & MO_BSWAP) == MO_TE) { - tcg_gen_concat32_i64(t64, lo, hi); + tcg_gen_concat_tl_i64(t64, lo, hi); } else { - tcg_gen_concat32_i64(t64, hi, lo); + tcg_gen_concat_tl_i64(t64, hi, lo); } save_state(dc); @@ -2635,8 +2670,8 @@ static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, } } -static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, - int insn, int rd) +static void __attribute__((unused)) +gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd) { DisasASI da = get_asi(dc, insn, MO_TEUQ); TCGv oldv; @@ -2657,88 +2692,6 @@ static void gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, } } -#elif !defined(CONFIG_USER_ONLY) -static void gen_ldda_asi(DisasContext *dc, TCGv addr, int insn, int rd) -{ - /* ??? Work around an apparent bug in Ubuntu gcc 4.8.2-10ubuntu2+12, - whereby "rd + 1" elicits "error: array subscript is above array". - Since we have already asserted that rd is even, the semantics - are unchanged. */ - TCGv lo = gen_dest_gpr(dc, rd | 1); - TCGv hi = gen_dest_gpr(dc, rd); - TCGv_i64 t64 = tcg_temp_new_i64(); - DisasASI da = get_asi(dc, insn, MO_TEUQ); - - switch (da.type) { - case GET_ASI_EXCP: - return; - case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_ld_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); - break; - default: - { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); - - save_state(dc); - gen_helper_ld_asi(t64, tcg_env, addr, r_asi, r_mop); - } - break; - } - - tcg_gen_extr_i64_i32(lo, hi, t64); - gen_store_gpr(dc, rd | 1, lo); - gen_store_gpr(dc, rd, hi); -} - -static void gen_stda_asi(DisasContext *dc, TCGv hi, TCGv addr, - int insn, int rd) -{ - DisasASI da = get_asi(dc, insn, MO_TEUQ); - TCGv lo = gen_load_gpr(dc, rd + 1); - TCGv_i64 t64 = tcg_temp_new_i64(); - - tcg_gen_concat_tl_i64(t64, lo, hi); - - switch (da.type) { - case GET_ASI_EXCP: - break; - case GET_ASI_DIRECT: - gen_address_mask(dc, addr); - tcg_gen_qemu_st_i64(t64, addr, da.mem_idx, da.memop | MO_ALIGN); - break; - case GET_ASI_BFILL: - /* Store 32 bytes of T64 to ADDR. */ - /* ??? The original qemu code suggests 8-byte alignment, dropping - the low bits, but the only place I can see this used is in the - Linux kernel with 32 byte alignment, which would make more sense - as a cacheline-style operation. */ - { - TCGv d_addr = tcg_temp_new(); - TCGv eight = tcg_constant_tl(8); - int i; - - tcg_gen_andi_tl(d_addr, addr, -8); - for (i = 0; i < 32; i += 8) { - tcg_gen_qemu_st_i64(t64, d_addr, da.mem_idx, da.memop); - tcg_gen_add_tl(d_addr, d_addr, eight); - } - } - break; - default: - { - TCGv_i32 r_asi = tcg_constant_i32(da.asi); - TCGv_i32 r_mop = tcg_constant_i32(MO_UQ); - - save_state(dc); - gen_helper_st_asi(tcg_env, addr, t64, r_asi, r_mop); - } - break; - } -} -#endif - static TCGv get_src1(DisasContext *dc, unsigned int insn) { unsigned int rs1 = GET_FIELD(insn, 13, 17);