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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id h1-20020a62b401000000b00690d255b5a1sm2427978pfn.217.2023.10.20.22.35.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 22:35:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v3 72/90] target/sparc: Move FSQRTq to decodetree Date: Fri, 20 Oct 2023 22:31:40 -0700 Message-Id: <20231021053158.278135-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231021053158.278135-1-richard.henderson@linaro.org> References: <20231021053158.278135-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::72a; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x72a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 39 +++++++++++++++++++++++---------------- 2 files changed, 24 insertions(+), 16 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index d8a49838a0..6994312909 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -247,6 +247,7 @@ FABSs 10 ..... 110100 00000 0 0000 1001 ..... @r_r2 FABSd 10 ..... 110100 00000 0 0000 1010 ..... @r_r2 FSQRTs 10 ..... 110100 00000 0 0010 1001 ..... @r_r2 FSQRTd 10 ..... 110100 00000 0 0010 1010 ..... @r_r2 +FSQRTq 10 ..... 110100 00000 0 0010 1011 ..... @r_r2 FdTOx 10 ..... 110100 00000 0 1000 0010 ..... @r_r2 FxTOd 10 ..... 110100 00000 0 1000 1000 ..... @r_r2 FiTOs 10 ..... 110100 00000 0 1100 0100 ..... @r_r2 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 38ad2034eb..2d594ddc9f 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -71,6 +71,7 @@ #define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) #define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) #define gen_helper_pdist ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fsqrtq ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -1682,18 +1683,6 @@ static void gen_fop_DDD(DisasContext *dc, int rd, int rs1, int rs2, gen_store_fpr_D(dc, rd, dst); } -static void gen_fop_QQ(DisasContext *dc, int rd, int rs, - void (*gen)(TCGv_ptr)) -{ - gen_op_load_fpr_QT1(QFPREG(rs)); - - gen(tcg_env); - gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); - - gen_op_store_QT0_fpr(QFPREG(rd)); - gen_update_fprs_dirty(dc, QFPREG(rd)); -} - #ifdef TARGET_SPARC64 static void gen_ne_fop_QQ(DisasContext *dc, int rd, int rs, void (*gen)(TCGv_ptr)) @@ -4962,6 +4951,27 @@ TRANS(FSQRTd, ALL, do_env_dd, a, gen_helper_fsqrtd) TRANS(FxTOd, 64, do_env_dd, a, gen_helper_fxtod) TRANS(FdTOx, 64, do_env_dd, a, gen_helper_fdtox) +static bool do_env_qq(DisasContext *dc, arg_r_r *a, + void (*func)(TCGv_env)) +{ + if (gen_trap_ifnofpu(dc)) { + return true; + } + if (gen_trap_float128(dc)) { + return true; + } + + gen_op_clear_ieee_excp_and_FTT(); + gen_op_load_fpr_QT1(QFPREG(a->rs)); + func(tcg_env); + gen_helper_check_ieee_exceptions(cpu_fsr, tcg_env); + gen_op_store_QT0_fpr(QFPREG(a->rd)); + gen_update_fprs_dirty(dc, QFPREG(a->rd)); + return advance_pc(dc); +} + +TRANS(FSQRTq, ALL, do_env_qq, a, gen_helper_fsqrtq) + static bool do_fff(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i32, TCGv_i32, TCGv_i32)) { @@ -5107,11 +5117,8 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x2a: /* fsqrtd */ case 0x82: /* V9 fdtox */ case 0x88: /* V9 fxtod */ - g_assert_not_reached(); /* in decodetree */ case 0x2b: /* fsqrtq */ - CHECK_FPU_FEATURE(dc, FLOAT128); - gen_fop_QQ(dc, rd, rs2, gen_helper_fsqrtq); - break; + g_assert_not_reached(); /* in decodetree */ case 0x41: /* fadds */ gen_fop_FFF(dc, rd, rs1, rs2, gen_helper_fadds); break;