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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id f4-20020a5d50c4000000b0032da319a27asm2117375wrt.9.2023.10.20.10.15.16 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 10:15:17 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Marcel Apfelbaum , "Michael S. Tsirkin" , Richard Henderson , Markus Armbruster , Bernhard Beschow , qemu-ppc@nongnu.org, =?utf-8?q?Herv=C3=A9_Poussineau?= , Paolo Bonzini , Eduardo Habkost , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 1/4] hw/i386/pc: Pass Error** argument to pc_basic_device_init() Date: Fri, 20 Oct 2023 19:15:05 +0200 Message-ID: <20231020171509.87839-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020171509.87839-1-philmd@linaro.org> References: <20231020171509.87839-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org pc_basic_device_init() creates devices which can fail, allow to propagate error to caller. Suggested-by: Markus Armbruster Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- include/hw/i386/pc.h | 5 +++-- hw/i386/pc.c | 7 +++++-- hw/i386/pc_piix.c | 2 +- hw/i386/pc_q35.c | 2 +- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index bec38cb92c..069c27368d 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -174,11 +174,12 @@ void pc_memory_init(PCMachineState *pcms, uint64_t pci_hole64_size); uint64_t pc_pci_hole64_start(void); DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); -void pc_basic_device_init(struct PCMachineState *pcms, +bool pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, ISADevice *rtc_state, bool create_fdctrl, - uint32_t hpet_irqs); + uint32_t hpet_irqs, + Error **errp); void pc_cmos_init(PCMachineState *pcms, BusState *ide0, BusState *ide1, ISADevice *s); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index f7ee638bec..2481c11e83 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1189,11 +1189,12 @@ static void pc_superio_init(ISABus *isa_bus, bool create_fdctrl, g_free(a20_line); } -void pc_basic_device_init(struct PCMachineState *pcms, +bool pc_basic_device_init(struct PCMachineState *pcms, ISABus *isa_bus, qemu_irq *gsi, ISADevice *rtc_state, bool create_fdctrl, - uint32_t hpet_irqs) + uint32_t hpet_irqs, + Error **errp) { int i; DeviceState *hpet = NULL; @@ -1291,6 +1292,8 @@ void pc_basic_device_init(struct PCMachineState *pcms, /* Super I/O */ pc_superio_init(isa_bus, create_fdctrl, pcms->i8042_enabled, pcms->vmport != ON_OFF_AUTO_ON); + + return true; } void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index e36a3262b2..0d9cdf773e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -320,7 +320,7 @@ static void pc_init1(MachineState *machine, /* init basic PC hardware */ pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, true, - 0x4); + 0x4, &error_fatal); pc_nic_init(pcmc, isa_bus, pci_bus); diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index a7386f2ca2..e4b05e3139 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -301,7 +301,7 @@ static void pc_q35_init(MachineState *machine) /* init basic PC hardware */ pc_basic_device_init(pcms, isa_bus, x86ms->gsi, rtc_state, !mc->no_floppy, - 0xff0104); + 0xff0104, &error_fatal); if (pcms->sata_enabled) { /* ahci and SATA device, for q35 1 ahci controller is built-in */