From patchwork Fri Oct 20 16:36:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 736275 Delivered-To: patch@linaro.org Received: by 2002:adf:dd81:0:b0:32d:baff:b0ca with SMTP id x1csp402202wrl; Fri, 20 Oct 2023 09:43:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQFc4NQYmfIJbGB3LvVuXuzm6MXaUodjGXDbApJkxIfz85iCPECs8pwCyJshM1svZQQvn7 X-Received: by 2002:a05:6122:179a:b0:49e:1eca:f847 with SMTP id o26-20020a056122179a00b0049e1ecaf847mr2684485vkf.15.1697820198812; Fri, 20 Oct 2023 09:43:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697820198; cv=none; d=google.com; s=arc-20160816; b=NuzNkwj65GHpM0eYAhcFBSksTsqMEVKEFAmtqFYvLkiqYcT+Yv5deasLgf3kJbkcH8 0yAOajSKw+vOy5jkviuHCpDfMi/2XGugoQiLbLUC4fS9N+lsG435ExjT1QhsVPcecoLm hX+vrDs3H+AXUC3FCSxEu4LXu05BnsFT4zFLe0sR31VegUK9sS9vSWcTJXhv7yutnLGb cpYkO5TfSVgc5NSRXf5R4IsVSziA8lpMaz2iWNK/AOic6WS17S0N4D9ZH4R1aZ4elAoL jsfHVJGA6XKukcoqi4hHvAnoXTgL5T4v6lgIhUtg+ex/Ut2tj+lNx75llX9lkQ5XzuwH pFmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=glBeQZnUhkWGnfluElBv8to+WC3WDtUU/ZpHqLDizi4=; fh=bHlQXYStbs05aY0EAyGaMfJbShY+ETfyh4guRCrz04Q=; b=f08bLTp23YviedlI3zHfOch7Lq9fFDjI1qz0X/DHaK5rCnwRuWl5lJN9ee5Hx7I83s +Pmv9pKpxDthmS0STV6XdgaZrBIVRwCv2uZmDt8eyz4FNuUF/Lp47jzKevNf2czxgoqW 7Dx25rgj9oYrgKtuQf6oVL0rCFqoadQAOHvsR+HWG6tKhmGRHNtFfCnxNNvLdvAEnWsU UAJFs+mbMCPv2VV6wu+THYSZT2Hpdk8QcREC/6xrasePRa9bJ0455Amk83ctENQWLXqX lWjLOUEeiQSRuPsyzUwbJr8x2unrVsTt1gV9IE4UbxNvZOhenyCF+9LZmiw/9o9ZlPgb Vxbw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fDHvC9DP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u10-20020a05620a454a00b007789b7247f2si1607691qkp.648.2023.10.20.09.43.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 20 Oct 2023 09:43:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fDHvC9DP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qtsWR-0005vv-7W; Fri, 20 Oct 2023 12:38:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qtsWN-0005ex-Es for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:48 -0400 Received: from mail-lj1-x22f.google.com ([2a00:1450:4864:20::22f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qtsWK-0002mp-QG for qemu-devel@nongnu.org; Fri, 20 Oct 2023 12:38:47 -0400 Received: by mail-lj1-x22f.google.com with SMTP id 38308e7fff4ca-2c5071165d5so1431991fa.0 for ; Fri, 20 Oct 2023 09:38:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697819922; x=1698424722; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=glBeQZnUhkWGnfluElBv8to+WC3WDtUU/ZpHqLDizi4=; b=fDHvC9DPADTuiIOKlKlbpT7vBiHa3xHKJ/ok/6A/jFojphktCLSzuxaDf3d2M+Ta5j cptXIlZg4GxZHXdEJemEAOJEX1Ixt220l8k4ZsUWZRpRB9hUWG13/x4656tzArpOAxNp GGy/ZUkDsJT+ee8yYiQ+NuKYfbeW+uX6TkglydNgUD1EfryPHUkXIv9fA4hwmbxxhWu4 N/kO4dObkLmBwl78n8hGfk1MXv/tV6iZcDPVdPxTYjcNPjCW3DK7Ow7oMZtLSh8jRLl7 1U106kO+wFlAFjuTdwwBR3Sn7/KYE7DPtB4FklUVzlgHcm4O2v1IiVUZNnwxc1UHCUDV 504Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697819922; x=1698424722; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=glBeQZnUhkWGnfluElBv8to+WC3WDtUU/ZpHqLDizi4=; b=rz8btUGBQbso7UfH/jzZXh3hdN3GrsoM1oLcL7H9tyAwBZD1hppa+H1mcSFbz34jnn mLhxvmaClyG0rRGnVTc9GCylN0lkLaEHhoHH5delQM51O2VVQgOoMQK6iMNbXtqn7P3w rk2P25UoE6K48sjM5o1IdAnOKzyE8cT8nyj897UQO9ur991xbZTZf9qa2Dm+t8kuIuuQ 5y+xdRMFAogTR5PjDLzzUZQFYs2hU7sW+qqv6ivEqa0gapMCUElJNWGmoqrHJLXekOOG /QoiDeMalg0RW/eWSQmwIhpIakQ/N9BehZYjL3XfXWOEbrVnyRkzcAFn7C9Y6r2uHA5p ZP+g== X-Gm-Message-State: AOJu0YwfFY0fZhVoN8MG1oNR9kuvmsueeBbrBEIWITlct4tkiYFkKY7E g0gGF7gww/yGfwRFEjP0Q6+WLdY7jjDEnCqa7CQ= X-Received: by 2002:ac2:4183:0:b0:507:9f51:acee with SMTP id z3-20020ac24183000000b005079f51aceemr1635568lfh.22.1697819922614; Fri, 20 Oct 2023 09:38:42 -0700 (PDT) Received: from m1x-phil.lan (tbo33-h01-176-171-212-97.dsl.sta.abo.bbox.fr. [176.171.212.97]) by smtp.gmail.com with ESMTPSA id j12-20020a170906050c00b00977eec7b7e8sm1809552eja.68.2023.10.20.09.38.40 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 09:38:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , Richard Henderson , Paolo Bonzini , Alistair Francis , qemu-arm@nongnu.org, qemu-riscv@nongnu.org, "Edgar E. Iglesias" , qemu-ppc@nongnu.org, Eduardo Habkost , "Michael S. Tsirkin" , qemu-s390x@nongnu.org, Peter Maydell , =?utf-8?q?Alex_Benn=C3=A9e?= , Zhao Liu , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Palmer Dabbelt , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei Subject: [PATCH 15/19] cpus: Replace first_cpu by qemu_get_cpu(0, TYPE_RISCV_CPU) Date: Fri, 20 Oct 2023 18:36:37 +0200 Message-ID: <20231020163643.86105-16-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020163643.86105-1-philmd@linaro.org> References: <20231020163643.86105-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::22f; envelope-from=philmd@linaro.org; helo=mail-lj1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Mechanical change using the following coccinelle script: @@ @@ - first_cpu + qemu_get_cpu(0, TYPE_RISCV_CPU) Signed-off-by: Philippe Mathieu-Daudé --- hw/riscv/boot.c | 2 +- target/riscv/arch_dump.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 1d004660d4..5e979f7b6a 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -437,7 +437,7 @@ void riscv_setup_direct_kernel(hwaddr kernel_addr, hwaddr fdt_addr) { CPUState *cs; - for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) { + for (cs = qemu_get_cpu(0, TYPE_RISCV_CPU); cs; cs = CPU_NEXT(cs)) { RISCVCPU *riscv_cpu = RISCV_CPU(cs); riscv_cpu->env.kernel_addr = kernel_addr; riscv_cpu->env.fdt_addr = fdt_addr; diff --git a/target/riscv/arch_dump.c b/target/riscv/arch_dump.c index 434c8a3dbb..4813d1ac1f 100644 --- a/target/riscv/arch_dump.c +++ b/target/riscv/arch_dump.c @@ -167,10 +167,10 @@ int cpu_get_dump_info(ArchDumpInfo *info, RISCVCPU *cpu; CPURISCVState *env; - if (first_cpu == NULL) { + if (qemu_get_cpu(0, TYPE_RISCV_CPU) == NULL) { return -1; } - cpu = RISCV_CPU(first_cpu); + cpu = RISCV_CPU(qemu_get_cpu(0, TYPE_RISCV_CPU)); env = &cpu->env; info->d_machine = EM_RISCV;