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[176.171.212.97]) by smtp.gmail.com with ESMTPSA id u10-20020a17090657ca00b009b8dbdd5203sm1666524ejr.107.2023.10.20.08.06.42 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Fri, 20 Oct 2023 08:06:43 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Laurent Vivier , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH 2/6] hw/m68k/mcf5206: Pass CPU using QOM link property Date: Fri, 20 Oct 2023 17:06:22 +0200 Message-ID: <20231020150627.56893-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231020150627.56893-1-philmd@linaro.org> References: <20231020150627.56893-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::631; envelope-from=philmd@linaro.org; helo=mail-ej1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Avoid the interrupt controller directly access the first cpu via the qemu_get_cpu() call. Pass it from the board code. Signed-off-by: Philippe Mathieu-Daudé Tested-by: Thomas Huth Reviewed-by: Thomas Huth --- hw/m68k/an5206.c | 2 ++ hw/m68k/mcf5206.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c index 11ae4c9795..f51c93088f 100644 --- a/hw/m68k/an5206.c +++ b/hw/m68k/an5206.c @@ -26,6 +26,8 @@ static void mcf5206_init(MemoryRegion *sysmem, uint32_t base) SysBusDevice *s; dev = qdev_new(TYPE_MCF5206_MBAR); + object_property_set_link(OBJECT(dev), "m68k-cpu", + OBJECT(first_cpu), &error_abort); s = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(s, &error_fatal); diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index 2ab1b4f059..f920ca2ceb 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -10,6 +10,7 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "cpu.h" +#include "hw/qdev-properties.h" #include "hw/boards.h" #include "hw/irq.h" #include "hw/m68k/mcf.h" @@ -601,13 +602,19 @@ static void mcf5206_mbar_realize(DeviceState *dev, Error **errp) s->timer[1] = m5206_timer_init(s->pic[10]); s->uart[0] = mcf_uart_init(s->pic[12], serial_hd(0)); s->uart[1] = mcf_uart_init(s->pic[13], serial_hd(1)); - s->cpu = M68K_CPU(qemu_get_cpu(0)); } +static Property mcf5206_mbar_properties[] = { + DEFINE_PROP_LINK("m68k-cpu", m5206_mbar_state, cpu, + TYPE_M68K_CPU, M68kCPU *), + DEFINE_PROP_END_OF_LIST(), +}; + static void mcf5206_mbar_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); + device_class_set_props(dc, mcf5206_mbar_properties); set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->desc = "MCF5206 system integration module"; dc->realize = mcf5206_mbar_realize;