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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id w17-20020a63f511000000b005b61a024ec7sm2176380pgh.74.2023.10.18.14.51.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 14:51:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: deller@gmx.de Subject: [PATCH 12/61] target/hppa: Introduce TYPE_HPPA64_CPU Date: Wed, 18 Oct 2023 14:50:46 -0700 Message-Id: <20231018215135.1561375-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231018215135.1561375-1-richard.henderson@linaro.org> References: <20231018215135.1561375-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Prepare for the qemu binary supporting both pa10 and pa20 at the same time. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/hppa/cpu-qom.h | 1 + target/hppa/cpu.h | 7 +++++++ target/hppa/cpu.c | 17 +++++++++++++++++ target/hppa/translate.c | 3 +++ 4 files changed, 28 insertions(+) diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index b96e0318c7..4a85ebf5e0 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -24,6 +24,7 @@ #include "qom/object.h" #define TYPE_HPPA_CPU "hppa-cpu" +#define TYPE_HPPA64_CPU "hppa64-cpu" OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 798d0c26d7..743fc90e14 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -239,10 +239,17 @@ struct ArchCPU { CPUHPPAState env; QEMUTimer *alarm_timer; + + bool is_pa20; }; #include "exec/cpu-all.h" +static inline bool hppa_is_pa20(HPPACPU *cpu) +{ + return cpu->is_pa20; +} + static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) { #ifdef CONFIG_USER_ONLY diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 1644297bf8..ed5b6afd10 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -218,9 +218,26 @@ static const TypeInfo hppa_cpu_type_info = { .class_init = hppa_cpu_class_init, }; +#ifdef TARGET_HPPA64 +static void hppa64_cpu_initfn(Object *obj) +{ + HPPACPU *cpu = HPPA_CPU(obj); + cpu->is_pa20 = true; +} + +static const TypeInfo hppa64_cpu_type_info = { + .name = TYPE_HPPA64_CPU, + .parent = TYPE_HPPA_CPU, + .instance_init = hppa64_cpu_initfn, +}; +#endif + static void hppa_cpu_register_types(void) { type_register_static(&hppa_cpu_type_info); +#ifdef TARGET_HPPA64 + type_register_static(&hppa64_cpu_type_info); +#endif } type_init(hppa_cpu_register_types) diff --git a/target/hppa/translate.c b/target/hppa/translate.c index f86ea9b9ca..9d6670f91c 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -262,6 +262,7 @@ typedef struct DisasContext { int mmu_idx; int privilege; bool psw_n_nonzero; + bool is_pa20; #ifdef CONFIG_USER_ONLY MemOp unalign; @@ -4087,10 +4088,12 @@ static bool trans_diag(DisasContext *ctx, arg_diag *a) static void hppa_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) { DisasContext *ctx = container_of(dcbase, DisasContext, base); + HPPACPU *cpu = HPPA_CPU(cs); int bound; ctx->cs = cs; ctx->tb_flags = ctx->base.tb->flags; + ctx->is_pa20 = cpu->is_pa20; #ifdef CONFIG_USER_ONLY ctx->privilege = MMU_IDX_TO_PRIV(MMU_USER_IDX);