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[176.171.218.149]) by smtp.gmail.com with ESMTPSA id q20-20020a170906145400b009c387ff67bdsm1795642ejc.22.2023.10.18.07.12.24 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 18 Oct 2023 07:12:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Eric Farman , Peter Xu , "Michael S. Tsirkin" , Halil Pasic , Jiaxun Yang , Strahinja Jankovic , Eduardo Habkost , Sergio Lopez , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell , Marcel Apfelbaum , Jason Wang , qemu-arm@nongnu.org, qemu-s390x@nongnu.org, Ilya Leoshkevich , Song Gao , Huacai Chen , Beniamino Galvani , Christian Borntraeger , Thomas Huth , David Hildenbrand , =?utf-8?q?Daniel_P=2E_Berrang=C3=A9?= , Paolo Bonzini Subject: [PATCH 04/12] hw/misc/allwinner-dramc: Do not use SysBus API to map local MMIO region Date: Wed, 18 Oct 2023 16:11:42 +0200 Message-ID: <20231018141151.87466-5-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231018141151.87466-1-philmd@linaro.org> References: <20231018141151.87466-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62a; envelope-from=philmd@linaro.org; helo=mail-ej1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There is no point in exposing an internal MMIO region via SysBus and directly mapping it in the very same device. Just map it without using the SysBus API. Signed-off-by: Philippe Mathieu-Daudé --- hw/misc/allwinner-r40-dramc.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/hw/misc/allwinner-r40-dramc.c b/hw/misc/allwinner-r40-dramc.c index 2cc0254a55..3d81ddb2e1 100644 --- a/hw/misc/allwinner-r40-dramc.c +++ b/hw/misc/allwinner-r40-dramc.c @@ -414,7 +414,6 @@ static void allwinner_r40_dramc_reset(DeviceState *dev) static void allwinner_r40_dramc_realize(DeviceState *dev, Error **errp) { AwR40DramCtlState *s = AW_R40_DRAMC(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(dev); if (!get_match_ddr(s->ram_size)) { error_report("%s: ram-size %u MiB is not supported", @@ -422,23 +421,23 @@ static void allwinner_r40_dramc_realize(DeviceState *dev, Error **errp) exit(1); } - /* R40 support max 2G memory but we only support up to 1G now. index 3 */ + /* R40 support max 2G memory but we only support up to 1G now. */ memory_region_init_io(&s->detect_cells, OBJECT(s), &allwinner_r40_detect_ops, s, "DRAMCELLS", 1 * GiB); - sysbus_init_mmio(sbd, &s->detect_cells); - sysbus_mmio_map_overlap(sbd, 3, s->ram_addr, 10); + memory_region_add_subregion_overlap(get_system_memory(), s->ram_addr, + &s->detect_cells, 10); memory_region_set_enabled(&s->detect_cells, false); /* * We only support DRAM size up to 1G now, so prepare a high memory page - * after 1G for dualrank detect. index = 4 + * after 1G for dualrank detect. */ memory_region_init_io(&s->dram_high, OBJECT(s), &allwinner_r40_dualrank_detect_ops, s, "DRAMHIGH", KiB); - sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->dram_high); - sysbus_mmio_map(SYS_BUS_DEVICE(s), 4, s->ram_addr + GiB); + memory_region_add_subregion(get_system_memory(), s->ram_addr + GiB, + &s->dram_high); } static void allwinner_r40_dramc_init(Object *obj)