diff mbox series

[20/20] target/sparc: Implement UDIV inline

Message ID 20231017064109.681935-21-richard.henderson@linaro.org
State New
Headers show
Series target/sparc: Cleanup condition codes etc | expand

Commit Message

Richard Henderson Oct. 17, 2023, 6:41 a.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/sparc/helper.h    |  1 -
 target/sparc/helper.c    | 29 +++++++---------------
 target/sparc/translate.c | 52 +++++++++++++++++++++++++++++++++++-----
 3 files changed, 54 insertions(+), 28 deletions(-)
diff mbox series

Patch

diff --git a/target/sparc/helper.h b/target/sparc/helper.h
index 12181d1106..624a8fdedf 100644
--- a/target/sparc/helper.h
+++ b/target/sparc/helper.h
@@ -27,7 +27,6 @@  DEF_HELPER_FLAGS_2(tick_set_limit, TCG_CALL_NO_RWG, void, ptr, i64)
 DEF_HELPER_1(debug, void, env)
 DEF_HELPER_1(save, void, env)
 DEF_HELPER_1(restore, void, env)
-DEF_HELPER_FLAGS_3(udiv, TCG_CALL_NO_WG, tl, env, tl, tl)
 DEF_HELPER_FLAGS_3(sdiv, TCG_CALL_NO_WG, tl, env, tl, tl)
 DEF_HELPER_3(udiv_cc, tl, env, tl, tl)
 DEF_HELPER_3(sdiv_cc, tl, env, tl, tl)
diff --git a/target/sparc/helper.c b/target/sparc/helper.c
index 3830d01634..1a900753d7 100644
--- a/target/sparc/helper.c
+++ b/target/sparc/helper.c
@@ -81,15 +81,14 @@  void helper_tick_set_limit(void *opaque, uint64_t limit)
 }
 #endif
 
-static target_ulong do_udiv(CPUSPARCState *env, target_ulong a,
-                            target_ulong b, int cc, uintptr_t ra)
+target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b)
 {
     target_ulong v, r;
     uint64_t x0 = (uint32_t)a | ((uint64_t)env->y << 32);
     uint32_t x1 = b;
 
     if (x1 == 0) {
-        cpu_raise_exception_ra(env, TT_DIV_ZERO, ra);
+        cpu_raise_exception_ra(env, TT_DIV_ZERO, GETPC());
     }
 
     x0 = x0 / x1;
@@ -99,29 +98,17 @@  static target_ulong do_udiv(CPUSPARCState *env, target_ulong a,
         v = r = UINT32_MAX;
     }
 
-    if (cc) {
-        env->cc_N = r;
-        env->cc_V = v;
-        env->cc_icc_Z = r;
-        env->cc_icc_C = 0;
+    env->cc_N = r;
+    env->cc_V = v;
+    env->cc_icc_Z = r;
+    env->cc_icc_C = 0;
 #ifdef TARGET_SPARC64
-        env->cc_xcc_Z = r;
-        env->cc_xcc_C = 0;
+    env->cc_xcc_Z = r;
+    env->cc_xcc_C = 0;
 #endif
-    }
     return r;
 }
 
-target_ulong helper_udiv(CPUSPARCState *env, target_ulong a, target_ulong b)
-{
-    return do_udiv(env, a, b, 0, GETPC());
-}
-
-target_ulong helper_udiv_cc(CPUSPARCState *env, target_ulong a, target_ulong b)
-{
-    return do_udiv(env, a, b, 1, GETPC());
-}
-
 static target_ulong do_sdiv(CPUSPARCState *env, target_ulong a,
                             target_ulong b, int cc, uintptr_t ra)
 {
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index b344422f8a..2c533a1998 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -576,11 +576,6 @@  static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
     gen_op_multiply(dst, src1, src2, 1);
 }
 
-static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
-{
-    gen_helper_udiv(dst, tcg_env, src1, src2);
-}
-
 static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
 {
     gen_helper_sdiv(dst, tcg_env, src1, src2);
@@ -3615,7 +3610,6 @@  TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL)
 TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl)
 TRANS(UMUL, MUL, do_arith, a, gen_op_umul, NULL)
 TRANS(SMUL, MUL, do_arith, a, gen_op_smul, NULL)
-TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL)
 TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL)
 TRANS(ADDC, ALL, do_arith, a, gen_op_addc, NULL)
 TRANS(SUBC, ALL, do_arith, a, gen_op_subc, NULL)
@@ -3642,6 +3636,52 @@  TRANS(ADDCcc, ALL, do_arith, a, gen_op_addccc, NULL)
 TRANS(SUBCcc, ALL, do_arith, a, gen_op_subccc, NULL)
 TRANS(MULScc, ALL, do_arith, a, gen_op_mulscc, NULL)
 
+static bool trans_UDIV(DisasContext *dc, arg_r_r_ri *a)
+{
+    TCGv_i64 t1, t2;
+    TCGv dst;
+
+    /* For simplicity, we under-decoded the rs2 form. */
+    if (!a->imm && a->rs2_or_imm & ~0x1f) {
+        return false;
+    }
+
+    if (unlikely(a->rs2_or_imm == 0)) {
+        gen_exception(dc, TT_DIV_ZERO);
+        return true;
+    }
+
+    if (a->imm) {
+        t2 = tcg_constant_i64((uint32_t)a->rs2_or_imm);
+    } else {
+        TCGLabel *lab;
+        TCGv_i32 n2;
+
+        finishing_insn(dc);
+        flush_cond(dc);
+
+        n2 = tcg_temp_new_i32();
+        tcg_gen_trunc_tl_i32(n2, cpu_regs[a->rs2_or_imm]);
+
+        lab = delay_exception(dc, TT_DIV_ZERO);
+        tcg_gen_brcondi_i32(TCG_COND_EQ, n2, 0, lab);
+
+        t2 = tcg_temp_new_i64();
+        tcg_gen_extu_tl_i64(t2, cpu_regs[a->rs2_or_imm]);
+    }
+
+    t1 = tcg_temp_new_i64();
+    tcg_gen_concat_tl_i64(t1, gen_load_gpr(dc, a->rs1), cpu_y);
+
+    tcg_gen_divu_i64(t1, t1, t2);
+    tcg_gen_umin_i64(t1, t1, tcg_constant_i64(UINT32_MAX));
+
+    dst = gen_dest_gpr(dc, a->rd);
+    tcg_gen_trunc_i64_tl(dst, t1);
+    gen_store_gpr(dc, a->rd, dst);
+    return advance_pc(dc);
+}
+
 static bool trans_UDIVX(DisasContext *dc, arg_r_r_ri *a)
 {
     TCGv dst, src1, src2;