@@ -180,5 +180,9 @@ SUBC 10 ..... 001100 ..... . ............. @r_r_ri
SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri
UDIVX 10 ..... 001101 ..... . ............. @r_r_ri
SDIVX 10 ..... 101101 ..... . ............. @r_r_ri
+UDIV 10 ..... 001110 ..... . ............. @r_r_ri
+UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri
+SDIV 10 ..... 001111 ..... . ............. @r_r_ri
+SDIVcc 10 ..... 011111 ..... . ............. @r_r_ri
Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7
@@ -655,6 +655,26 @@ static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
gen_helper_sdivx(dst, tcg_env, src1, src2);
}
+static void gen_op_udiv(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_udiv(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_sdiv(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_udivcc(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_udiv_cc(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_sdivcc(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_sdiv_cc(dst, tcg_env, src1, src2);
+}
+
// 1
static void gen_op_eval_ba(TCGv dst)
{
@@ -2869,6 +2889,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
# define avail_64(C) false
#endif
#define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
+#define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV)
#define avail_GL(C) ((C)->def->features & CPU_FEATURE_GL)
#define avail_HYPV(C) ((C)->def->features & CPU_FEATURE_HYPV)
#define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
@@ -4166,6 +4187,17 @@ static bool do_arith(DisasContext *dc, arg_r_r_ri *a,
return do_cc_arith(dc, a, -1, func, funci);
}
+static bool do_flags_arith(DisasContext *dc, arg_r_r_ri *a, int cc_op,
+ void (*func)(TCGv, TCGv, TCGv))
+{
+ if (do_arith(dc, a, func, NULL)) {
+ /* Assume FUNC has set env->cc_op and all cc_foo variables. */
+ dc->cc_op = cc_op;
+ return true;
+ }
+ return false;
+}
+
static bool trans_OR(DisasContext *dc, arg_r_r_ri *a)
{
/* For simplicity, we under-decoded the rs2 form. */
@@ -4201,6 +4233,8 @@ TRANS(UMUL, MUL, do_arith, a, gen_op_umul, NULL)
TRANS(SMUL, MUL, do_arith, a, gen_op_smul, NULL)
TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL)
TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL)
+TRANS(UDIV, DIV, do_arith, a, gen_op_udiv, NULL)
+TRANS(SDIV, DIV, do_arith, a, gen_op_sdiv, NULL)
TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL)
TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl)
@@ -4212,6 +4246,8 @@ TRANS(ORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_orc_tl, NULL)
TRANS(XORNcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_eqv_tl, NULL)
TRANS(UMULcc, MUL, do_cc_arith, a, CC_OP_LOGIC, gen_op_umul, NULL)
TRANS(SMULcc, MUL, do_cc_arith, a, CC_OP_LOGIC, gen_op_smul, NULL)
+TRANS(UDIVcc, DIV, do_flags_arith, a, CC_OP_DIV, gen_op_udivcc)
+TRANS(SDIVcc, DIV, do_flags_arith, a, CC_OP_DIV, gen_op_sdivcc)
static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm)
{
@@ -4695,35 +4731,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
#endif
} else if (xop < 0x36) {
if (xop < 0x20) {
- cpu_src1 = get_src1(dc, insn);
- cpu_src2 = get_src2(dc, insn);
- switch (xop & ~0x10) {
- case 0xe: /* udiv */
- CHECK_IU_FEATURE(dc, DIV);
- if (xop & 0x10) {
- gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- dc->cc_op = CC_OP_DIV;
- } else {
- gen_helper_udiv(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- }
- break;
- case 0xf: /* sdiv */
- CHECK_IU_FEATURE(dc, DIV);
- if (xop & 0x10) {
- gen_helper_sdiv_cc(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- dc->cc_op = CC_OP_DIV;
- } else {
- gen_helper_sdiv(cpu_dst, tcg_env, cpu_src1,
- cpu_src2);
- }
- break;
- default:
- goto illegal_insn;
- }
- gen_store_gpr(dc, rd, cpu_dst);
+ goto illegal_insn;
} else {
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/insns.decode | 4 +++ target/sparc/translate.c | 66 ++++++++++++++++++++++----------------- 2 files changed, 41 insertions(+), 29 deletions(-)