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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jf4-20020a170903268400b001ca21e05c69sm629150plb.109.2023.10.16.23.13.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 23:13:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 33/90] target/sparc: Move SUBC to decodetree Date: Mon, 16 Oct 2023 23:11:47 -0700 Message-Id: <20231017061244.681584-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231017061244.681584-1-richard.henderson@linaro.org> References: <20231017061244.681584-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 28 ++++++++++++++++++++++++---- 2 files changed, 26 insertions(+), 4 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c114a13f1d..64f5885e67 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -176,5 +176,7 @@ UMUL 10 ..... 001010 ..... . ............. @r_r_ri UMULcc 10 ..... 011010 ..... . ............. @r_r_ri SMUL 10 ..... 001011 ..... . ............. @r_r_ri SMULcc 10 ..... 011011 ..... . ............. @r_r_ri +SUBC 10 ..... 001100 ..... . ............. @r_r_ri +SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index b6ec7d5cfd..30eb9bf94b 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4236,6 +4236,30 @@ static bool trans_ADDCcc(DisasContext *dc, arg_r_r_ri *a) return advance_pc(dc); } +static bool trans_SUBC(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + + if (src2 == NULL) { + return false; + } + gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd), + gen_load_gpr(dc, a->rs1), src2, false); + return advance_pc(dc); +} + +static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a) +{ + TCGv src2 = gen_rs2_or_imm(dc, a->imm, a->rs2_or_imm); + + if (src2 == NULL) { + return false; + } + gen_op_subx_int(dc, gen_dest_gpr(dc, a->rd), + gen_load_gpr(dc, a->rs1), src2, true); + return advance_pc(dc); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4660,10 +4684,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { - case 0xc: /* subx, V9 subc */ - gen_op_subx_int(dc, cpu_dst, cpu_src1, cpu_src2, - (xop & 0x10)); - break; #ifdef TARGET_SPARC64 case 0xd: /* V9 udivx */ gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);