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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id jf4-20020a170903268400b001ca21e05c69sm629150plb.109.2023.10.16.23.13.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Oct 2023 23:13:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk Subject: [PATCH v2 31/90] target/sparc: Move MULX to decodetree Date: Mon, 16 Oct 2023 23:11:45 -0700 Message-Id: <20231017061244.681584-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231017061244.681584-1-richard.henderson@linaro.org> References: <20231017061244.681584-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, T_SPF_HELO_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 1 + target/sparc/translate.c | 6 +----- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index abcee27fd4..d9474d2a20 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -171,5 +171,6 @@ XORN 10 ..... 000111 ..... . ............. @r_r_ri XORNcc 10 ..... 010111 ..... . ............. @r_r_ri ADDC 10 ..... 001000 ..... . ............. @r_r_ri ADDCcc 10 ..... 011000 ..... . ............. @r_r_ri +MULX 10 ..... 001001 ..... . ............. @r_r_ri Tcc 10 0 cond:4 111010 rs1:5 imm:1 cc:1 00000 rs2_or_imm:7 diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 27375c74ec..b3ce3947f3 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -4183,6 +4183,7 @@ TRANS(SUB, ALL, do_arith, a, tcg_gen_sub_tl, tcg_gen_subi_tl) TRANS(ANDN, ALL, do_arith, a, tcg_gen_andc_tl, NULL) TRANS(ORN, ALL, do_arith, a, tcg_gen_orc_tl, NULL) TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL) +TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl) TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL) TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl) @@ -4654,11 +4655,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src1 = get_src1(dc, insn); cpu_src2 = get_src2(dc, insn); switch (xop & ~0x10) { -#ifdef TARGET_SPARC64 - case 0x9: /* V9 mulx */ - tcg_gen_mul_i64(cpu_dst, cpu_src1, cpu_src2); - break; -#endif case 0xa: /* umul */ CHECK_IU_FEATURE(dc, MUL); gen_op_umul(cpu_dst, cpu_src1, cpu_src2);