From patchwork Fri Oct 13 21:28:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 733321 Delivered-To: patch@linaro.org Received: by 2002:a5d:54d1:0:b0:31d:da82:a3b4 with SMTP id x17csp1680119wrv; Fri, 13 Oct 2023 14:37:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IETUilLB2G/kavpAeGos7kOuAABhPRaJXphay6oom+iRbJkjUmhtNV3mfwQHWv4Zr147h3X X-Received: by 2002:a05:6830:1050:b0:6c0:7bab:3457 with SMTP id b16-20020a056830105000b006c07bab3457mr28576979otp.20.1697233055681; Fri, 13 Oct 2023 14:37:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697233055; cv=none; d=google.com; s=arc-20160816; b=zqpl0bzRWnbA6ob0ZyIZMWBXjt7k7c0E2hql37AYPsvzFBR/nrVzxn0GOefhc1mcSq MAztPCTFwk6kecEB/jKsnNMTO1BvM2IZNhkcVSqZ/eh4+FsWLoPyP7Qo99W6ldgTuJ4S 2g2DcAffKH/kpy/0D6UQUD7R5hbmhZ/9dIO7zolagQVZVhejdXay7XTyXB73xJ+nURxT uMTtr4k+bbXhTOQ3LdQZOa1aKn/wHFc4qYU/n2AHlTil8VJ5V7hY2VgNhxsrf7QZknvt V5Zay1fNBKaU5RGfqi67LCUSmrhuVVUtB241gYd5ftDttSERAyWMbdZq0aEMKY0pMoPv /RPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Qe1tGpaO7hygRq2SclkhM8aLa2f7jO8gj6MYlNzdmFs=; fh=OY/jf0qYEhT53LcIJp8d/e39mN3vEzshkseI36O8N8s=; b=ISX7gJPk/Apf2/3AVlMD4PKzvneepP9jz8+r4dQgv5Kt4yK2gtxnQBrXmne7cuSTCS 2LLQLDZCQBufTeJ65InyIJZNDqtekbM+EIn2W1lX91hrYM7xLcwIRIFoeG+k4k+6YdTk Yzk8eaYY94TEh7y1vq36imHQqTC6AAelhDlH2qNzDmysBsGCTSTLLzVO0VXvGlNAfBOc jGHez2e7XUErSuGVig2pQhcV5TgbT3w6Zdwi0Z8MkR1Td0jD8P3NWuG/vjLOXlTwQ3Nn LGDi5bNRuk/stFRyA6cIbcczXipRfwwEEGgF81A4U6oXNux7FEeZ1OZsiDhZ6GtY/RCi y6vA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yoQmtFFF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j16-20020ac85c50000000b004199160e55esi1754027qtj.756.2023.10.13.14.37.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Fri, 13 Oct 2023 14:37:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yoQmtFFF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qrPpT-0000sz-2k; Fri, 13 Oct 2023 17:36:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qrPpR-0000d6-8l for qemu-devel@nongnu.org; Fri, 13 Oct 2023 17:36:17 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qrPpE-0002Tq-DZ for qemu-devel@nongnu.org; Fri, 13 Oct 2023 17:36:16 -0400 Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-6b1d1099a84so1119879b3a.1 for ; Fri, 13 Oct 2023 14:36:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1697232963; x=1697837763; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Qe1tGpaO7hygRq2SclkhM8aLa2f7jO8gj6MYlNzdmFs=; b=yoQmtFFF0UUww13rWD8tsD4bA4HoesxCQ5pNfdbOm8XFy3HfDLMtPxxJSz9xwBwOs3 VDdGgn8rOgCCjK3CWCc0PLO1DECEvmnQmN5FgCFXq/wO7yWIRlFUR5kqVodtQnexaFJn Ozk/bbmmsLQzvaVRXBvW2x/3L+gzm83Z3e2FdLjRDBoLDfTQkL+ZMmLLTrq5UF5/hCKm 71cY1n3KY1cIrLR9SJHnm7DAZPUHxmt6Irp9CHe+44SaIyhSg6PIhPR0IEHn4/syr0ky LDN699ucsRsdLYoYXpSybHw5YEGDmCN6wGKAJeiXJlkblLMR629zTFis3+MNpY6IJmUt Q4zQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697232963; x=1697837763; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Qe1tGpaO7hygRq2SclkhM8aLa2f7jO8gj6MYlNzdmFs=; b=uWGghWVZmOWNeC3p/Vg0v//KOjcD77txN48syU/GlTcXDsION/KD/pJF1aREOfdLqC WwqsQLgKCaUgZu5zE9EGNUXRty1k8MJ/VBkzzJaG5mKivStJLoHLCoeHDwhDyxHmDI2t EIcqncbfdaV2E+Le497CyOWeyWmWOm9copZpvFiYJvoBpuNWNO9TYu0MW22TneRdRk7J tPFlg0xngvsEqGii3twMUPLqFasPcjGYf5DjKm8zceKxI3ZbHv1a/2W1ownQo4U67joM odKikDZMs/7/mmcdp6EGShkGbZqH0HGGMPAkRq9oc4kiD5Fr2kAIDLb4emSQSE6rtEbz 1Ydg== X-Gm-Message-State: AOJu0YyurLrPJYcWI2+SiQSEDcLYTQlOY4WtoLUg7QcIxuKurDu/8JiY twLItpKZWrcCVCjboEOmJ2QVvJuE8WN8mEXcZ2Y= X-Received: by 2002:a05:6a00:1691:b0:693:3cbc:3d8e with SMTP id k17-20020a056a00169100b006933cbc3d8emr31480929pfc.0.1697232962755; Fri, 13 Oct 2023 14:36:02 -0700 (PDT) Received: from stoup.. ([71.212.149.95]) by smtp.gmail.com with ESMTPSA id v127-20020a626185000000b0068790c41ca2sm1123984pfb.27.2023.10.13.14.36.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:36:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 82/85] target/sparc: Move FPCMP* to decodetree Date: Fri, 13 Oct 2023 14:28:43 -0700 Message-Id: <20231013212846.165724-83-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 9 ++++ target/sparc/translate.c | 94 +++++++++++++++++---------------------- 2 files changed, 50 insertions(+), 53 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index c5d6f46737..9333c8ba3b 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -321,6 +321,15 @@ FCMPEq 10 000 cc:2 110101 rs1:5 0 0101 0111 rs2:5 BMASK 10 ..... 110110 ..... 0 0001 1001 ..... @r_r_r + FPCMPLE16 10 ..... 110110 ..... 0 0010 0000 ..... @r_r_r + FPCMPNE16 10 ..... 110110 ..... 0 0010 0010 ..... @r_r_r + FPCMPGT16 10 ..... 110110 ..... 0 0010 1000 ..... @r_r_r + FPCMPEQ16 10 ..... 110110 ..... 0 0010 1010 ..... @r_r_r + FPCMPLE32 10 ..... 110110 ..... 0 0010 0100 ..... @r_r_r + FPCMPNE32 10 ..... 110110 ..... 0 0010 0110 ..... @r_r_r + FPCMPGT32 10 ..... 110110 ..... 0 0010 1100 ..... @r_r_r + FPCMPEQ32 10 ..... 110110 ..... 0 0010 1110 ..... @r_r_r + FMUL8x16 10 ..... 110110 ..... 0 0011 0001 ..... @r_r_r FMUL8x16AU 10 ..... 110110 ..... 0 0011 0011 ..... @r_r_r FMUL8x16AL 10 ..... 110110 ..... 0 0011 0101 ..... @r_r_r diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 81d274448a..1a9fa18d64 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -77,7 +77,14 @@ #define gen_helper_fpmerge ({ g_assert_not_reached(); NULL; }) #define gen_helper_fexpand ({ g_assert_not_reached(); NULL; }) #define gen_helper_pdist ({ g_assert_not_reached(); NULL; }) -#define gen_helper_fsqrtq ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpeq16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpne16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmple16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpgt16 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpeq32 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpne32 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmple32 ({ g_assert_not_reached(); NULL; }) +#define gen_helper_fcmpgt32 ({ g_assert_not_reached(); NULL; }) #define FSR_LDXFSR_MASK ({ qemu_build_not_reached(); 0; }) #define FSR_LDXFSR_OLDMASK ({ qemu_build_not_reached(); 0; }) # ifdef CONFIG_USER_ONLY @@ -4930,6 +4937,37 @@ TRANS(FPACK32, VIS1, do_ddd, a, gen_op_fpack32) TRANS(FALIGNDATAg, VIS1, do_ddd, a, gen_op_faligndata) TRANS(BSHUFFLE, VIS2, do_ddd, a, gen_op_bshuffle) +static bool do_rdd(DisasContext *dc, arg_r_r_r *a, + void (*func)(TCGv_i64, TCGv_i64, TCGv_i64)) +{ +#ifdef TARGET_SPARC64 + TCGv_i64 dst, src1, src2; + + if (gen_trap_ifnofpu(dc)) { + return true; + } + + dst = gen_dest_gpr(dc, a->rd); + src1 = gen_load_fpr_D(dc, a->rs1); + src2 = gen_load_fpr_D(dc, a->rs2); + func(dst, src1, src2); + gen_store_gpr(dc, a->rd, dst); + return advance_pc(dc); +#else + g_assert_not_reached(); +#endif +} + +TRANS(FPCMPLE16, VIS1, do_rdd, a, gen_helper_fcmple16) +TRANS(FPCMPNE16, VIS1, do_rdd, a, gen_helper_fcmpne16) +TRANS(FPCMPGT16, VIS1, do_rdd, a, gen_helper_fcmpgt16) +TRANS(FPCMPEQ16, VIS1, do_rdd, a, gen_helper_fcmpeq16) + +TRANS(FPCMPLE32, VIS1, do_rdd, a, gen_helper_fcmple32) +TRANS(FPCMPNE32, VIS1, do_rdd, a, gen_helper_fcmpne32) +TRANS(FPCMPGT32, VIS1, do_rdd, a, gen_helper_fcmpgt32) +TRANS(FPCMPEQ32, VIS1, do_rdd, a, gen_helper_fcmpeq32) + static bool do_env_ddd(DisasContext *dc, arg_r_r_r *a, void (*func)(TCGv_i64, TCGv_env, TCGv_i64, TCGv_i64)) { @@ -5209,11 +5247,9 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) } else if (xop == 0x36) { #ifdef TARGET_SPARC64 /* VIS */ - TCGv_i64 cpu_src1_64, cpu_src2_64, cpu_dst_64; + TCGv_i64 cpu_src1_64, cpu_dst_64; TCGv_i32 cpu_dst_32; - TCGv cpu_dst = tcg_temp_new(); int opf = GET_FIELD_SP(insn, 5, 13); - int rs1 = GET_FIELD(insn, 13, 17); int rs2 = GET_FIELD(insn, 27, 31); int rd = GET_FIELD(insn, 2, 6); @@ -5289,63 +5325,15 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) case 0x03a: /* VIS I fpack32 */ case 0x048: /* VIS I faligndata */ case 0x04c: /* VIS II bshuffle */ - g_assert_not_reached(); /* in decodetree */ case 0x020: /* VIS I fcmple16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmple16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x022: /* VIS I fcmpne16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpne16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x024: /* VIS I fcmple32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmple32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x026: /* VIS I fcmpne32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpne32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x028: /* VIS I fcmpgt16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpgt16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02a: /* VIS I fcmpeq16 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpeq16(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02c: /* VIS I fcmpgt32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpgt32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; case 0x02e: /* VIS I fcmpeq32 */ - CHECK_FPU_FEATURE(dc, VIS1); - cpu_src1_64 = gen_load_fpr_D(dc, rs1); - cpu_src2_64 = gen_load_fpr_D(dc, rs2); - gen_helper_fcmpeq32(cpu_dst, cpu_src1_64, cpu_src2_64); - gen_store_gpr(dc, rd, cpu_dst); - break; + g_assert_not_reached(); /* in decodetree */ case 0x03b: /* VIS I fpack16 */ CHECK_FPU_FEATURE(dc, VIS1); cpu_src1_64 = gen_load_fpr_D(dc, rs2);