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([71.212.149.95]) by smtp.gmail.com with ESMTPSA id b185-20020a6334c2000000b0058988954686sm70753pga.90.2023.10.13.14.29.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Oct 2023 14:29:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 31/85] target/sparc: Move TADD, TSUB, MULS to decodetree Date: Fri, 13 Oct 2023 14:27:52 -0700 Message-Id: <20231013212846.165724-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson --- target/sparc/insns.decode | 5 +++++ target/sparc/translate.c | 47 +++++++++++++++++---------------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/target/sparc/insns.decode b/target/sparc/insns.decode index 35e7905bfe..2aae7d9514 100644 --- a/target/sparc/insns.decode +++ b/target/sparc/insns.decode @@ -187,3 +187,8 @@ UDIV 10 ..... 001110 ..... . ............. @r_r_ri UDIVcc 10 ..... 011110 ..... . ............. @r_r_ri SDIV 10 ..... 001111 ..... . ............. @r_r_ri SDIVcc 10 ..... 011111 ..... . ............. @r_r_ri +TADDcc 10 ..... 100000 ..... . ............. @r_r_ri +TSUBcc 10 ..... 100001 ..... . ............. @r_r_ri +TADDccTV 10 ..... 100010 ..... . ............. @r_r_ri +TSUBccTV 10 ..... 100011 ..... . ............. @r_r_ri +MULScc 10 ..... 100100 ..... . ............. @r_r_ri diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 1c335fb826..5f5c24b112 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -655,6 +655,16 @@ static void gen_op_sdiv(TCGv dst, TCGv src1, TCGv src2) gen_helper_sdiv(dst, tcg_env, src1, src2); } +static void gen_op_taddcctv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_taddcctv(dst, tcg_env, src1, src2); +} + +static void gen_op_tsubcctv(TCGv dst, TCGv src1, TCGv src2) +{ + gen_helper_tsubcctv(dst, tcg_env, src1, src2); +} + // 1 static void gen_op_eval_ba(TCGv dst) { @@ -4191,6 +4201,10 @@ TRANS(UMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_umul, NULL) TRANS(SMULcc, ALL, do_cc_arith, a, CC_OP_LOGIC, gen_op_smul, NULL) TRANS(UDIVcc, ALL, do_cc_arith, a, CC_OP_DIV, gen_op_udiv, NULL) TRANS(SDIVcc, ALL, do_cc_arith, a, CC_OP_DIV, gen_op_sdiv, NULL) +TRANS(TADDcc, ALL, do_cc_arith, a, CC_OP_TADD, gen_op_add_cc, NULL) +TRANS(TSUBcc, ALL, do_cc_arith, a, CC_OP_TSUB, gen_op_sub_cc, NULL) +TRANS(TADDccTV, ALL, do_cc_arith, a, CC_OP_TADDTV, gen_op_taddcctv, NULL) +TRANS(TSUBccTV, ALL, do_cc_arith, a, CC_OP_TSUBTV, gen_op_tsubcctv, NULL) static TCGv gen_rs2_or_imm(DisasContext *dc, bool imm, int rs2_or_imm) { @@ -4253,6 +4267,12 @@ static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a) return advance_pc(dc); } +static bool trans_MULScc(DisasContext *dc, arg_r_r_ri *a) +{ + update_psr(dc); + return do_cc_arith(dc, a, CC_OP_ADD, gen_op_mulscc, NULL); +} + #define CHECK_IU_FEATURE(dc, FEATURE) \ if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \ goto illegal_insn; @@ -4680,36 +4700,11 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn) cpu_src2 = get_src2(dc, insn); switch (xop) { case 0x20: /* taddcc */ - gen_op_add_cc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_TADD); - dc->cc_op = CC_OP_TADD; - break; case 0x21: /* tsubcc */ - gen_op_sub_cc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_TSUB); - dc->cc_op = CC_OP_TSUB; - break; case 0x22: /* taddcctv */ - gen_helper_taddcctv(cpu_dst, tcg_env, - cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - dc->cc_op = CC_OP_TADDTV; - break; case 0x23: /* tsubcctv */ - gen_helper_tsubcctv(cpu_dst, tcg_env, - cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - dc->cc_op = CC_OP_TSUBTV; - break; case 0x24: /* mulscc */ - update_psr(dc); - gen_op_mulscc(cpu_dst, cpu_src1, cpu_src2); - gen_store_gpr(dc, rd, cpu_dst); - tcg_gen_movi_i32(cpu_cc_op, CC_OP_ADD); - dc->cc_op = CC_OP_ADD; - break; + goto illegal_insn; /* in decodetree */ #ifndef TARGET_SPARC64 case 0x25: /* sll */ if (IS_IMM) { /* immediate */