@@ -181,3 +181,5 @@ SMUL 10 ..... 001011 ..... . ............. @r_r_ri
SMULcc 10 ..... 011011 ..... . ............. @r_r_ri
SUBC 10 ..... 001100 ..... . ............. @r_r_ri
SUBCcc 10 ..... 011100 ..... . ............. @r_r_ri
+UDIVX 10 ..... 001101 ..... . ............. @r_r_ri
+SDIVX 10 ..... 101101 ..... . ............. @r_r_ri
@@ -53,6 +53,8 @@
#define gen_helper_write_softint(E, S) qemu_build_not_reached()
#define gen_helper_saved ({ qemu_build_not_reached(); NULL; })
#define gen_helper_restored ({ qemu_build_not_reached(); NULL; })
+#define gen_helper_udivx(D, E, A, B) qemu_build_not_reached()
+#define gen_helper_sdivx(D, E, A, B) qemu_build_not_reached()
#endif
/* Dynamic PC, must exit to main loop. */
@@ -633,6 +635,16 @@ static void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
gen_op_multiply(dst, src1, src2, 1);
}
+static void gen_op_udivx(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_udivx(dst, tcg_env, src1, src2);
+}
+
+static void gen_op_sdivx(TCGv dst, TCGv src1, TCGv src2)
+{
+ gen_helper_sdivx(dst, tcg_env, src1, src2);
+}
+
// 1
static void gen_op_eval_ba(TCGv dst)
{
@@ -4152,6 +4164,8 @@ TRANS(XORN, ALL, do_arith, a, tcg_gen_eqv_tl, NULL)
TRANS(MULX, 64, do_arith, a, tcg_gen_mul_tl, tcg_gen_muli_tl)
TRANS(UMUL, ALL, do_arith, a, gen_op_umul, NULL)
TRANS(SMUL, ALL, do_arith, a, gen_op_smul, NULL)
+TRANS(UDIVX, 64, do_arith, a, gen_op_udivx, NULL)
+TRANS(SDIVX, 64, do_arith, a, gen_op_sdivx, NULL)
TRANS(ADDcc, ALL, do_cc_arith, a, CC_OP_ADD, gen_op_add_cc, NULL)
TRANS(ANDcc, ALL, do_cc_arith, a, CC_OP_LOGIC, tcg_gen_and_tl, tcg_gen_andi_tl)
@@ -4224,7 +4238,6 @@ static bool trans_SUBCcc(DisasContext *dc, arg_r_r_ri *a)
gen_load_gpr(dc, a->rs1), src2, true);
return advance_pc(dc);
}
-
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@@ -4649,11 +4662,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
cpu_src1 = get_src1(dc, insn);
cpu_src2 = get_src2(dc, insn);
switch (xop & ~0x10) {
-#ifdef TARGET_SPARC64
- case 0xd: /* V9 udivx */
- gen_helper_udivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);
- break;
-#endif
case 0xe: /* udiv */
if (xop & 0x10) {
gen_helper_udiv_cc(cpu_dst, tcg_env, cpu_src1,
@@ -4789,10 +4797,6 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
gen_store_gpr(dc, rd, dst);
break;
}
- case 0x2d: /* V9 sdivx */
- gen_helper_sdivx(cpu_dst, tcg_env, cpu_src1, cpu_src2);
- gen_store_gpr(dc, rd, cpu_dst);
- break;
case 0x2e: /* V9 popc */
tcg_gen_ctpop_tl(cpu_dst, cpu_src2);
gen_store_gpr(dc, rd, cpu_dst);
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/sparc/insns.decode | 2 ++ target/sparc/translate.c | 24 ++++++++++++++---------- 2 files changed, 16 insertions(+), 10 deletions(-)