diff mbox series

[02/85] configs: Enable MTTCG for sparc, sparc64

Message ID	20231013212846.165724-3-richard.henderson@linaro.org
State	Superseded
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: mark.cave-ayland@ilande.co.uk, atar4qemu@gmail.com Subject: [PATCH 02/85] configs: Enable MTTCG for sparc, sparc64 Date: Fri, 13 Oct 2023 14:27:23 -0700 Message-Id: <20231013212846.165724-3-richard.henderson@linaro.org> In-Reply-To: <20231013212846.165724-1-richard.henderson@linaro.org> References: <20231013212846.165724-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	target/sparc: Convert to decodetree \| expand [00/85] target/sparc: Convert to decodetree [01/85] target/sparc: Set TCG_GUEST_DEFAULT_MO [02/85] configs: Enable MTTCG for sparc, sparc64 [03/85] target/sparc: Remove always-set cpu features [04/85] target/sparc: Add decodetree infrastructure [05/85] target/sparc: Define AM_CHECK for sparc32 [06/85] target/sparc: Move CALL to decodetree [07/85] target/sparc: Move BPcc and Bicc to decodetree [08/85] target/sparc: Move BPr to decodetree [09/85] target/sparc: Move FBPfcc and FBfcc to decodetree [10/85] target/sparc: Merge gen_cond with only caller [11/85] target/sparc: Merge gen_fcond with only caller [12/85] target/sparc: Merge gen_branch_[an] with only caller [13/85] target/sparc: Pass DisasCompare to advance_jump_cond [14/85] target/sparc: Move SETHI to decodetree [15/85] target/sparc: Move Tcc to decodetree [16/85] target/sparc: Move RDASR, STBAR, MEMBAR to decodetree [17/85] target/sparc: Move RDPSR, RDHPR to decodetree [18/85] target/sparc: Move RDWIM, RDPR to decodetree [19/85] target/sparc: Move RDTBR, FLUSHW to decodetree [20/85] target/sparc: Move WRASR to decodetree [21/85] target/sparc: Move WRPSR, SAVED, RESTORED to decodetree [22/85] target/sparc: Move WRWIM, WRPR to decodetree [23/85] target/sparc: Move WRTBR, WRHPR to decodetree [24/85] target/sparc: Move basic arithmetic to decodetree [25/85] target/sparc: Move ADDC to decodetree [26/85] target/sparc: Move MULX to decodetree [27/85] target/sparc: Move UMUL, SMUL to decodetree [28/85] target/sparc: Move SUBC to decodetree [29/85] target/sparc: Move UDIVX, SDIVX to decodetree [30/85] target/sparc: Move UDIV, SDIV to decodetree [31/85] target/sparc: Move TADD, TSUB, MULS to decodetree [32/85] target/sparc: Move SLL, SRL, SRA to decodetree [33/85] target/sparc: Move MOVcc, MOVR to decodetree [34/85] target/sparc: Move POPC to decodetree [35/85] target/sparc: Convert remaining v8 coproc insns to decodetree [36/85] target/sparc: Move JMPL, RETT, RETURN to decodetree [37/85] target/sparc: Move FLUSH, SAVE, RESTORE to decodetree [38/85] target/sparc: Move DONE, RETRY to decodetree [39/85] target/sparc: Split out resolve_asi [40/85] target/sparc: Drop ifdef around get_asi and friends [41/85] target/sparc: Split out ldst functions with asi pre-computed [42/85] target/sparc: Use tcg_gen_qemu_{ld, st}_i128 for GET_ASI_DTWINX [43/85] target/sparc: Move simple integer load/store to decodetree [44/85] target/sparc: Move asi integer load/store to decodetree [45/85] target/sparc: Move LDSTUB, LDSTUBA to decodetree [46/85] target/sparc: Move SWAP, SWAPA to decodetree [47/85] target/sparc: Move CASA, CASXA to decodetree [48/85] target/sparc: Move PREFETCH, PREFETCHA to decodetree [49/85] target/sparc: Split out fp ldst functions with asi precomputed [50/85] target/sparc: Move simple fp load/store to decodetree [51/85] target/sparc: Move asi fp load/store to decodetree [52/85] target/sparc: Move LDFSR, STFSR to decodetree [53/85] target/sparc: Merge LDFSR, LDXFSR implementations [54/85] target/sparc: Move EDGE* to decodetree [55/85] target/sparc: Move ARRAY* to decodetree [56/85] target/sparc: Move ADDRALIGN* to decodetree [57/85] target/sparc: Move BMASK to decodetree [58/85] target/sparc: Move FMOVS, FNEGS, FABSS, FSRCS, FNOTS to decodetree [59/85] target/sparc: Move FMOVD, FNEGD, FABSD, FSRCD, FNOTD to decodetree [60/85] target/sparc: Use tcg_gen_vec_{add,sub}* [61/85] target/sparc: Move gen_ne_fop_FFF insns to decodetree [62/85] target/sparc: Move gen_ne_fop_DDD insns to decodetree [63/85] target/sparc: Move PDIST to decodetree [64/85] target/sparc: Move gen_gsr_fop_DDD insns to decodetree [65/85] target/sparc: Move gen_fop_FF insns to decodetree [66/85] target/sparc: Move gen_fop_DD insns to decodetree [67/85] target/sparc: Move FSQRTq to decodetree [68/85] target/sparc: Move gen_fop_FFF insns to decodetree [69/85] target/sparc: Move gen_fop_DDD insns to decodetree [70/85] target/sparc: Move gen_fop_QQQ insns to decodetree [71/85] target/sparc: Move FSMULD to decodetree [72/85] target/sparc: Move FDMULQ to decodetree [73/85] target/sparc: Move gen_fop_FD insns to decodetree [74/85] target/sparc: Move FiTOd, FsTOd, FsTOx to decodetree [75/85] target/sparc: Move FqTOs, FqTOi to decodetree [76/85] target/sparc: Move FqTOd, FqTOx to decodetree [77/85] target/sparc: Move FiTOq, FsTOq to decodetree [78/85] target/sparc: Move FdTOq, FxTOq to decodetree [79/85] target/sparc: Move FMOVq, FNEGq, FABSq to decodetree [80/85] target/sparc: Move FMOVR, FMOVcc, FMOVfcc to decodetree [81/85] target/sparc: Convert FCMP, FCMPE to decodetree [82/85] target/sparc: Move FPCMP* to decodetree [83/85] target/sparc: Move FPACK16, FPACKFIX to decodetree [84/85] target/sparc: Convert FZERO, FONE to decodetree [85/85] target/sparc: Remove disas_sparc_legacy

Commit Message

Richard Henderson Oct. 13, 2023, 9:27 p.m. UTC

This will be of small comfort to sparc64, because both
sun4u and sun4v board models force max_cpus = 1.
But it does enable actual smp for sparc32 sun4m.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 configs/targets/sparc-softmmu.mak   | 1 +
 configs/targets/sparc64-softmmu.mak | 1 +
 2 files changed, 2 insertions(+)

diff mbox series

Patch

diff --git a/configs/targets/sparc-softmmu.mak b/configs/targets/sparc-softmmu.mak
index 454eb35499..a5d9200382 100644
--- a/configs/targets/sparc-softmmu.mak
+++ b/configs/targets/sparc-softmmu.mak
@@ -1,2 +1,3 @@ 
 TARGET_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y
diff --git a/configs/targets/sparc64-softmmu.mak b/configs/targets/sparc64-softmmu.mak
index d3f8a3b710..36ca64ec41 100644
--- a/configs/targets/sparc64-softmmu.mak
+++ b/configs/targets/sparc64-softmmu.mak
@@ -1,3 +1,4 @@ 
 TARGET_ARCH=sparc64
 TARGET_BASE_ARCH=sparc
 TARGET_BIG_ENDIAN=y
+TARGET_SUPPORTS_MTTCG=y