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[176.131.211.232]) by smtp.gmail.com with ESMTPSA id x20-20020a170906299400b00997c1d125fasm11157488eje.170.2023.10.12.05.19.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Thu, 12 Oct 2023 05:19:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Andrey Smirnov , qemu-arm@nongnu.org, Peter Maydell , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 2/8] hw/pci-host/designware: Initialize root function in host bridge realize Date: Thu, 12 Oct 2023 14:18:50 +0200 Message-ID: <20231012121857.31873-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231012121857.31873-1-philmd@linaro.org> References: <20231012121857.31873-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::634; envelope-from=philmd@linaro.org; helo=mail-ej1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org There are no root function properties exposed by the host bridge, so using a 2-step QOM creation isn't really useful. Simplify by creating the root function when the host bridge is realized. Signed-off-by: Philippe Mathieu-Daudé --- hw/pci-host/designware.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 304eca1b5c..692e0731cd 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -707,6 +707,10 @@ static void designware_pcie_host_realize(DeviceState *dev, Error **errp) "pcie-bus-address-space"); pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s); + object_initialize_child(OBJECT(dev), "root", &s->root, + TYPE_DESIGNWARE_PCIE_ROOT); + qdev_prop_set_int32(DEVICE(&s->root), "addr", PCI_DEVFN(0, 0)); + qdev_prop_set_bit(DEVICE(&s->root), "multifunction", false); qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); } @@ -736,22 +740,11 @@ static void designware_pcie_host_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_designware_pcie_host; } -static void designware_pcie_host_init(Object *obj) -{ - DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj); - DesignwarePCIERoot *root = &s->root; - - object_initialize_child(obj, "root", root, TYPE_DESIGNWARE_PCIE_ROOT); - qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); - qdev_prop_set_bit(DEVICE(root), "multifunction", false); -} - static const TypeInfo designware_pcie_types[] = { { .name = TYPE_DESIGNWARE_PCIE_HOST, .parent = TYPE_PCI_HOST_BRIDGE, .instance_size = sizeof(DesignwarePCIEHost), - .instance_init = designware_pcie_host_init, .class_init = designware_pcie_host_class_init, }, { .name = TYPE_DESIGNWARE_PCIE_ROOT,