From patchwork Tue Oct 10 09:28:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 731445 Delivered-To: patch@linaro.org Received: by 2002:a5d:574c:0:b0:31d:da82:a3b4 with SMTP id q12csp1641786wrw; Tue, 10 Oct 2023 02:33:41 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF7nUQotcfky0J2MQq5RKEz5SgrIWjPGvTALzhyhtM5xf7ZqE8NMn31B8VHYZpZbSGMflC9 X-Received: by 2002:a0c:dd90:0:b0:65b:177b:a430 with SMTP id v16-20020a0cdd90000000b0065b177ba430mr17563029qvk.47.1696930421367; Tue, 10 Oct 2023 02:33:41 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1696930421; cv=none; d=google.com; s=arc-20160816; b=GFypxojjLDABo4vFSp/B/3VuzGLTQwx5f8+B6JXeCVYDPfmCFgX7uERPRLd2PpDhbW CDu4MBThfq75lcVue2v1RJ+JTb6yGSbC5h5QveCQQKJWWxPHVSstl3ZCsegmtG0xMpz2 wC9xUyP0mJL76ypcFqVp+nN+qzS0mKxiKKGK+Rjc/ElcpWq1VaYUod5Kkm1aivhgyOiP YA2PvJumvV28YpeXcEsRJqbUuC0mkG//exccmiEPjbmXyULOG66j0V+rN2vdZqzTUW+3 nhC3XVxMGqCZEDROD8dZg4av1wlDhL54QXcu0uxkft2TQorWLlSPjrAwILg08T5hLSFB pv8g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7/Dazi2VzLCUVkcADynMQnmNFinEpKaq76+gzFIU2vQ=; fh=iupQBrmerAoZOw8v6swRnyYBx+6KhbF7AbBF1Jawaz4=; b=P2aBuyixx2kHvKhm0im8Sh4rQU+9sUvvTBoeBw9800TDAQf3FLHEpRcrC3t5aj9rhK NmL1g6rmq/0Hc/J8cnpU7psrooxe4pWG3qmc9Bo2Lbvh3qVAqHhv4V1ffvaYPFcjlUe+ ZQ+4+6pDqOye46bPs533V0KeTbD9uNIE0QRG2V2C5PA/0F6Osfv2XaLviVTSuQzfiBv9 jQ8481HFutHXJIOCRtj3UsB9W1KDCik0PjpxuhheLR4P8/GMNSBDyc6eQsLZuxPRcHPL j96ya2pNx7vtoQSwfZEPWuY3oRKR3N7dHSQZzCBlJli6x1mIQwmMHtcg34oORIFQ1omC 4Bvg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dFh3/cNe"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n19-20020a0cdc93000000b006581f5f151csi7337649qvk.77.2023.10.10.02.33.41 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 10 Oct 2023 02:33:41 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="dFh3/cNe"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qq94x-0001ML-Nj; Tue, 10 Oct 2023 05:31:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qq94F-0000ky-EM for qemu-devel@nongnu.org; Tue, 10 Oct 2023 05:30:22 -0400 Received: from mail-ej1-x635.google.com ([2a00:1450:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qq94B-00083f-8W for qemu-devel@nongnu.org; Tue, 10 Oct 2023 05:30:19 -0400 Received: by mail-ej1-x635.google.com with SMTP id a640c23a62f3a-9b1ebc80d0aso925420266b.0 for ; Tue, 10 Oct 2023 02:30:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1696930211; x=1697535011; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7/Dazi2VzLCUVkcADynMQnmNFinEpKaq76+gzFIU2vQ=; b=dFh3/cNe+On7xhRCW8nuZ6RCMK46Ax5YXxIYv8IepPwWGll2phVbZL1lwX3fwSwFLF xjudtckYYeoqxE6hVpJqNbVXj8klHG5Ouh8TDp8hCXdPlRW13IyVMYrUvNr/BYyEOjI2 QL7OS3stmrQ63c+syx/e0FrQRDQ5EE1Te5isVHGG/Z6Kzd6rl40Cuo5O/tX9ApxovvhR A5sD1XX2m5Go6t7XfauS9xfMQ0tUtSpYJKrsr2VRsVrEVGFZe9k4BUct4SnaZLm7qIHw 8zZv94AXXErcyAwbUM2Hl+ex1zlDdA8msxG6GkW2DwRMn2WLByjHbb6h2N33/ZFFUwdo 2DYA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1696930211; x=1697535011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7/Dazi2VzLCUVkcADynMQnmNFinEpKaq76+gzFIU2vQ=; b=Xxc/PSk1wEdyMbXVC5n13bHdXVfiOp9cJdHj1V4DSE/vIYF2M+b3BBIRLgJh35tgvE r9+qEnclzBWI7iXQmm1RphYRXPtCYpKH0ZEZA3j5LgfYjNL8XtiYy2/lvbtHfz/dIfqB dIJ8tcowcOe3jH5qFics1nijHqcytCLo9uDdhBdFY3GFFB7omNI1XB3helsrwfV/ZuLn vimbEWjO5CIxQJnZkEqIOCPlnFE9OtjpRjGvYyko/hVVKEIV2VYwr2jzIWotWdZyB7sf DA/b/Mk7euK7tE8crq9dTvsFXnVR6hNgeOH9tvJ5oid7d0qo/FIymWjLkL6rDUZglOef /yng== X-Gm-Message-State: AOJu0YwcfeNf25Yk7x4Vvif0zmJ27Us4/fR1JKAbIi+tH88yfMBZOh6P asUELa8VPKAlf3njqV9r44hECUiiM+MolWDVi1LkJw== X-Received: by 2002:a17:907:2704:b0:9ae:961a:de81 with SMTP id w4-20020a170907270400b009ae961ade81mr14194859ejk.27.1696930210993; Tue, 10 Oct 2023 02:30:10 -0700 (PDT) Received: from m1x-phil.lan (aif79-h01-176-172-113-148.dsl.sta.abo.bbox.fr. [176.172.113.148]) by smtp.gmail.com with ESMTPSA id n12-20020a170906378c00b009ade1a4f795sm8142642ejc.168.2023.10.10.02.30.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:30:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 08/18] target/openrisc: Declare QOM definitions in 'cpu-qom.h' Date: Tue, 10 Oct 2023 11:28:50 +0200 Message-ID: <20231010092901.99189-9-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::635; envelope-from=philmd@linaro.org; helo=mail-ej1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu.h" contains the target specific declarations. A heterogeneous setup need to access target agnostic declarations (at least the QOM ones, to instantiate the objects). Our convention is to add such target agnostic QOM declarations in the "target/foo/cpu-qom.h" header. Extract QOM definitions from "cpu.h" to "cpu-qom.h". Signed-off-by: Philippe Mathieu-Daudé --- target/openrisc/cpu-qom.h | 36 ++++++++++++++++++++++++++++++++++++ target/openrisc/cpu.h | 26 +------------------------- 2 files changed, 37 insertions(+), 25 deletions(-) create mode 100644 target/openrisc/cpu-qom.h diff --git a/target/openrisc/cpu-qom.h b/target/openrisc/cpu-qom.h new file mode 100644 index 0000000000..d1930acb74 --- /dev/null +++ b/target/openrisc/cpu-qom.h @@ -0,0 +1,36 @@ +/* + * QEMU OpenRISC CPU QOM header (target agnostic) + * + * Copyright (c) 2011-2012 Jia Liu + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#ifndef QEMU_OPENRISC_CPU_QOM_H +#define QEMU_OPENRISC_CPU_QOM_H + +#include "hw/core/cpu.h" +#include "qom/object.h" + +#define TYPE_OPENRISC_CPU "or1k-cpu" + +OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) + +#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU +#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX + +/** + * OpenRISCCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_phases: The parent class' reset phase handlers. + * + * A OpenRISC CPU model. + */ +struct OpenRISCCPUClass { + CPUClass parent_class; + + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +#endif diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 334997e9a1..2dccd67378 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -20,33 +20,12 @@ #ifndef OPENRISC_CPU_H #define OPENRISC_CPU_H +#include "cpu-qom.h" #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" -#include "hw/core/cpu.h" -#include "qom/object.h" #define TCG_GUEST_DEFAULT_MO (0) -#define TYPE_OPENRISC_CPU "or1k-cpu" - -OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) - -/** - * OpenRISCCPUClass: - * @parent_realize: The parent class' realize handler. - * @parent_phases: The parent class' reset phase handlers. - * - * A OpenRISC CPU model. - */ -struct OpenRISCCPUClass { - /*< private >*/ - CPUClass parent_class; - /*< public >*/ - - DeviceRealize parent_realize; - ResettablePhases parent_phases; -}; - #define TARGET_INSN_START_EXTRA_WORDS 1 enum { @@ -308,7 +287,6 @@ struct ArchCPU { CPUOpenRISCState env; }; - void cpu_openrisc_list(void); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, int flags); int openrisc_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); @@ -343,8 +321,6 @@ void cpu_openrisc_count_start(OpenRISCCPU *cpu); void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #endif -#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU -#define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU #include "exec/cpu-all.h"