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[176.172.113.148]) by smtp.gmail.com with ESMTPSA id e5-20020a17090681c500b00993a37aebc5sm8090599ejx.50.2023.10.10.02.31.29 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 10 Oct 2023 02:31:33 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: David Hildenbrand , "Michael S. Tsirkin" , Song Gao , =?utf-8?q?C=C3=A9dric_Le_Goater?= , =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= , Laurent Vivier , Bastian Koppelmann , qemu-arm@nongnu.org, Jiaxun Yang , Ilya Leoshkevich , Yoshinori Sato , Paolo Bonzini , Weiwei Li , Nicholas Piggin , qemu-riscv@nongnu.org, "Edgar E. Iglesias" , Bin Meng , Yanan Wang , Palmer Dabbelt , Alistair Francis , Aleksandar Rikalo , Daniel Henrique Barboza , Marek Vasut , Peter Maydell , qemu-ppc@nongnu.org, Michael Rolnik , Max Filippov , Mark Cave-Ayland , Laurent Vivier , Stafford Horne , Thomas Huth , Chris Wulff , Sergio Lopez , Xiaojuan Yang , Richard Henderson , Liu Zhiwei , Artyom Tarasenko , Daniel Henrique Barboza , Eduardo Habkost , Brian Cain , Marcel Apfelbaum , Aurelien Jarno , qemu-s390x@nongnu.org Subject: [PATCH 18/18] target/sparc: Make SPARC_CPU common to new SPARC32_CPU/SPARC64_CPU types Date: Tue, 10 Oct 2023 11:29:00 +0200 Message-ID: <20231010092901.99189-19-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20231010092901.99189-1-philmd@linaro.org> References: <20231010092901.99189-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::62e; envelope-from=philmd@linaro.org; helo=mail-ej1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org "target/foo/cpu-qom.h" can not use any target specific definitions. Currently "target/sparc/cpu-qom.h" defines TYPE_SPARC_CPU depending on the sparc(32)/sparc64 build type. This doesn't scale in a heterogeneous context where we need to access both types concurrently. In order to do that, introduce the new SPARC32_CPU / SPARC64_CPU types, both inheriting a common TYPE_SPARC_CPU base type. Keep the current CPU types registered in sparc_register_cpudef_type() as 32 or 64-bit, depending on the binary built. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Mark Cave-Ayland --- target/sparc/cpu-qom.h | 9 ++++----- target/sparc/cpu.h | 3 +++ target/sparc/cpu.c | 12 +++++++++++- 3 files changed, 18 insertions(+), 6 deletions(-) diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index 86b24a254a..d08fbd4ddc 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -23,13 +23,12 @@ #include "hw/core/cpu.h" #include "qom/object.h" -#ifdef TARGET_SPARC64 -#define TYPE_SPARC_CPU "sparc64-cpu" -#else #define TYPE_SPARC_CPU "sparc-cpu" -#endif +#define TYPE_SPARC32_CPU "sparc32-cpu" +#define TYPE_SPARC64_CPU "sparc64-cpu" -OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) +OBJECT_DECLARE_CPU_TYPE(SPARC32CPU, SPARCCPUClass, SPARC32_CPU) +OBJECT_DECLARE_CPU_TYPE(SPARC64CPU, SPARCCPUClass, SPARC64_CPU) #define SPARC_CPU_TYPE_SUFFIX "-" TYPE_SPARC_CPU #define SPARC_CPU_TYPE_NAME(model) model SPARC_CPU_TYPE_SUFFIX diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 924e83b9ce..0f94e5a442 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -12,6 +12,9 @@ #define TARGET_DPREGS 32 #endif +/* Abstract QOM SPARC CPU, not exposed to other targets */ +OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) + /*#define EXCP_INTERRUPT 0x100*/ /* Windowed register indexes. */ diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 1e66413e94..7d060ba488 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -934,6 +934,12 @@ static const TypeInfo sparc_cpu_types[] = { .abstract = true, .class_size = sizeof(SPARCCPUClass), .class_init = sparc_cpu_class_init, + }, { + .name = TYPE_SPARC32_CPU, + .parent = TYPE_SPARC_CPU, + }, { + .name = TYPE_SPARC64_CPU, + .parent = TYPE_SPARC_CPU, } }; @@ -950,7 +956,11 @@ static void sparc_register_cpudef_type(const struct sparc_def_t *def) char *typename = sparc_cpu_type_name(def->name); TypeInfo ti = { .name = typename, - .parent = TYPE_SPARC_CPU, +#ifdef TARGET_SPARC64 + .parent = TYPE_SPARC64_CPU, +#else + .parent = TYPE_SPARC32_CPU, +#endif .class_init = sparc_cpu_cpudef_class_init, .class_data = (void *)def, };