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[212.78.193.212]) by smtp.gmail.com with ESMTPSA id z15-20020a170906240f00b0099bd1ce18fesm6723198eja.10.2023.09.18.09.04.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 18 Sep 2023 09:04:02 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Laurent Vivier , Paolo Bonzini , Max Filippov , David Hildenbrand , Peter Xu , Anton Johansson , Peter Maydell , kvm@vger.kernel.org, Marek Vasut , David Gibson , Brian Cain , Yoshinori Sato , "Edgar E . Iglesias" , Claudio Fontana , Daniel Henrique Barboza , Artyom Tarasenko , Marcelo Tosatti , qemu-ppc@nongnu.org, Liu Zhiwei , Aurelien Jarno , Ilya Leoshkevich , Daniel Henrique Barboza , Bastian Koppelmann , =?utf-8?q?C=C3=A9dric_?= =?utf-8?q?Le_Goater?= , Alistair Francis , Alessandro Di Federico , Song Gao , Marcel Apfelbaum , Chris Wulff , "Michael S. Tsirkin" , Alistair Francis , Fabiano Rosas , qemu-s390x@nongnu.org, Yanan Wang , Luc Michel , Weiwei Li , Bin Meng , Stafford Horne , Xiaojuan Yang , "Daniel P . Berrange" , Thomas Huth , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , qemu-arm@nongnu.org, Jiaxun Yang , Richard Henderson , Aleksandar Rikalo , Bernhard Beschow , Mark Cave-Ayland , qemu-riscv@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Nicholas Piggin , Greg Kurz , Michael Rolnik , Eduardo Habkost , Markus Armbruster , Palmer Dabbelt Subject: [PATCH 12/22] target/mips: Create clock *after* accelerator vCPU is realized Date: Mon, 18 Sep 2023 18:02:45 +0200 Message-ID: <20230918160257.30127-13-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230918160257.30127-1-philmd@linaro.org> References: <20230918160257.30127-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::532; envelope-from=philmd@linaro.org; helo=mail-ed1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Architecture specific hardware doesn't have a particular dependency on the accelerator vCPU (created with cpu_exec_realizefn), and can be initialized *after* the vCPU is realized. Doing so allows further generic API simplification (in few commits). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/mips/cpu.c | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 0aea69aaf9..7c81e6c356 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -464,20 +464,6 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(dev); Error *local_err = NULL; - if (!clock_get(cpu->clock)) { -#ifndef CONFIG_USER_ONLY - if (!qtest_enabled()) { - g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); - - warn_report("CPU input clock is not connected to any output clock, " - "using default frequency of %s.", cpu_freq_str); - } -#endif - /* Initialize the frequency in case the clock remains unconnected. */ - clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); - } - mips_cp0_period_set(cpu); - cpu_exec_realizefn(cs, &local_err); if (local_err != NULL) { error_propagate(errp, local_err); @@ -492,6 +478,20 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) fpu_init(env, env->cpu_model); mvp_init(env); + if (!clock_get(cpu->clock)) { +#ifndef CONFIG_USER_ONLY + if (!qtest_enabled()) { + g_autofree char *cpu_freq_str = freq_to_str(CPU_FREQ_HZ_DEFAULT); + + warn_report("CPU input clock is not connected to any output clock, " + "using default frequency of %s.", cpu_freq_str); + } +#endif + /* Initialize the frequency in case the clock remains unconnected. */ + clock_set_hz(cpu->clock, CPU_FREQ_HZ_DEFAULT); + } + mips_cp0_period_set(cpu); + mcc->parent_realize(dev, errp); cpu_reset(cs); }