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([71.212.131.115]) by smtp.gmail.com with ESMTPSA id n21-20020aa79055000000b0068fde95aa93sm4871708pfo.135.2023.09.16.14.42.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 16 Sep 2023 14:42:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: philmd@linaro.org, anjo@rev.ng Subject: [PATCH v3 39/39] accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG Date: Sat, 16 Sep 2023 14:41:23 -0700 Message-Id: <20230916214123.525796-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230916214123.525796-1-richard.henderson@linaro.org> References: <20230916214123.525796-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé We don't need to expose these TCG-specific methods to the whole code base. Register them as AccelClass handlers, they will be called by the generic accel_cpu_[un]realize() methods. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20230915190009.68404-6-philmd@linaro.org> Signed-off-by: Richard Henderson --- accel/tcg/internal-target.h | 3 +++ include/exec/cpu-all.h | 2 -- accel/tcg/tcg-all.c | 2 ++ cpu-target.c | 8 -------- 4 files changed, 5 insertions(+), 10 deletions(-) diff --git a/accel/tcg/internal-target.h b/accel/tcg/internal-target.h index 932bbe4b63..4e36cf858e 100644 --- a/accel/tcg/internal-target.h +++ b/accel/tcg/internal-target.h @@ -80,6 +80,9 @@ bool tb_invalidate_phys_page_unwind(tb_page_addr_t addr, uintptr_t pc); void cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t host_pc); +bool tcg_exec_realizefn(CPUState *cpu, Error **errp); +void tcg_exec_unrealizefn(CPUState *cpu); + /* Return the current PC from CPU, which may be cached in TB. */ static inline vaddr log_pc(CPUState *cpu, const TranslationBlock *tb) { diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 6c1db14842..5340907cfd 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -410,8 +410,6 @@ static inline bool tlb_hit(uint64_t tlb_addr, vaddr addr) /* accel/tcg/cpu-exec.c */ int cpu_exec(CPUState *cpu); -bool tcg_exec_realizefn(CPUState *cpu, Error **errp); -void tcg_exec_unrealizefn(CPUState *cpu); /* Validate correct placement of CPUArchState. */ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, parent_obj) != 0); diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index b32e0b80ec..a40e0aee37 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -227,6 +227,8 @@ static void tcg_accel_class_init(ObjectClass *oc, void *data) AccelClass *ac = ACCEL_CLASS(oc); ac->name = "tcg"; ac->init_machine = tcg_init_machine; + ac->realize_cpu = tcg_exec_realizefn; + ac->unrealize_cpu = tcg_exec_unrealizefn; ac->allowed = &tcg_allowed; ac->gdbstub_supported_sstep_flags = tcg_gdbstub_supported_sstep_flags; diff --git a/cpu-target.c b/cpu-target.c index b928bbed50..1a8e730bed 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -140,11 +140,6 @@ void cpu_exec_realizefn(CPUState *cpu, Error **errp) return; } - /* NB: errp parameter is unused currently */ - if (tcg_enabled()) { - tcg_exec_realizefn(cpu, errp); - } - /* Wait until cpu initialization complete before exposing cpu. */ cpu_list_add(cpu); @@ -190,9 +185,6 @@ void cpu_exec_unrealizefn(CPUState *cpu) * accel_cpu_unrealize, which may free fields using call_rcu. */ accel_cpu_unrealize(cpu); - if (tcg_enabled()) { - tcg_exec_unrealizefn(cpu); - } } /*