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Thu, 31 Aug 2023 05:59:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-s390x@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-block@nongnu.org, Michael Tokarev , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo Subject: [PULL 29/41] hw/mips: spelling fixes Date: Thu, 31 Aug 2023 14:56:31 +0200 Message-ID: <20230831125646.67855-30-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230831125646.67855-1-philmd@linaro.org> References: <20230831125646.67855-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=philmd@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Michael Tokarev Signed-off-by: Michael Tokarev Reviewed-by: Philippe Mathieu-Daudé Message-ID: <20230823065335.1919380-7-mjt@tls.msk.ru> Signed-off-by: Philippe Mathieu-Daudé --- hw/mips/malta.c | 2 +- target/mips/tcg/msa_helper.c | 12 ++++++------ target/mips/tcg/mxu_translate.c | 6 +++--- target/mips/cpu-defs.c.inc | 2 +- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f9618fa5f5..16e9c4773f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -627,7 +627,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; - /* Bus endianess is always reversed */ + /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN #define cpu_to_gt32(x) (x) #else diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index c8597b9e30..c314a74397 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -803,9 +803,9 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) * | HADD_S.H | Vector Signed Horizontal Add (halfword) | * | HADD_S.W | Vector Signed Horizontal Add (word) | * | HADD_S.D | Vector Signed Horizontal Add (doubleword) | - * | HADD_U.H | Vector Unigned Horizontal Add (halfword) | - * | HADD_U.W | Vector Unigned Horizontal Add (word) | - * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) | + * | HADD_U.H | Vector Unsigned Horizontal Add (halfword) | + * | HADD_U.W | Vector Unsigned Horizontal Add (word) | + * | HADD_U.D | Vector Unsigned Horizontal Add (doubleword) | * +---------------+----------------------------------------------------------+ */ @@ -3452,9 +3452,9 @@ void helper_msa_mulv_d(CPUMIPSState *env, * | HSUB_S.H | Vector Signed Horizontal Subtract (halfword) | * | HSUB_S.W | Vector Signed Horizontal Subtract (word) | * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) | - * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword) | - * | HSUB_U.W | Vector Unigned Horizontal Subtract (word) | - * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) | + * | HSUB_U.H | Vector Unsigned Horizontal Subtract (halfword) | + * | HSUB_U.W | Vector Unsigned Horizontal Subtract (word) | + * | HSUB_U.D | Vector Unsigned Horizontal Subtract (doubleword) | * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) | * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) | * | SUBS_S.W | Vector Signed Saturated Subtract (of Signed) (word) | diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index e662acd5df..cfcd8ac9bc 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2977,14 +2977,14 @@ static void gen_mxu_Q8ADD(DisasContext *ctx) * to another one in XRc, with zero extending * to 16-bit and put results as packed 16-bit data * into XRa and XRd. - * aptn2 manages action add or subract of pairs of data. + * aptn2 manages action add or subtract of pairs of data. * * Q8ACCE XRa, XRb, XRc, XRd, aptn2 * Add/subtract quadruple of 8-bit packed in XRb * to another one in XRc, with zero extending * to 16-bit and accumulate results as packed 16-bit data * into XRa and XRd. - * aptn2 manages action add or subract of pairs of data. + * aptn2 manages action add or subtract of pairs of data. */ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate) { @@ -4056,7 +4056,7 @@ static void gen_mxu_s32sfl(DisasContext *ctx) /* * Q8SAD XRa, XRd, XRb, XRc - * Typical SAD opration for motion estimation. + * Typical SAD operation for motion estimation. */ static void gen_mxu_q8sad(DisasContext *ctx) { diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 03185d9aa0..c0c389c59a 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -1045,7 +1045,7 @@ static void mvp_init(CPUMIPSState *env) return; } - /* MVPConf1 implemented, TLB sharable, no gating storage support, + /* MVPConf1 implemented, TLB shareable, no gating storage support, programmable cache partitioning implemented, number of allocatable and shareable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */