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[176.172.10.165]) by smtp.gmail.com with ESMTPSA id e25-20020a50ec99000000b0052a404e5929sm5669edr.66.2023.08.23.07.55.49 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 23 Aug 2023 07:55:50 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , "Edgar E. Iglesias" , Paolo Bonzini , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 1/8] tcg/tcg-op: Document bswap16_i32() byte pattern Date: Wed, 23 Aug 2023 16:55:35 +0200 Message-ID: <20230823145542.79633-2-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230823145542.79633-1-philmd@linaro.org> References: <20230823145542.79633-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::535; envelope-from=philmd@linaro.org; helo=mail-ed1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- tcg/tcg-op.c | 32 ++++++++++++++++++++++++-------- 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 7aadb37756..c1b9a3e34c 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1021,6 +1021,15 @@ void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg) } } +/* + * bswap16_i32: 16-bit byte swap on the low bits of a 32-bit value. + * + * flags + * Byte pattern: bswap16_i32(..ab) -> .aba (TCG_BSWAP_IZ) + * bswap16_i32(xxab) -> ..ba (TCG_BSWAP_OZ) + * bswap16_i32(xxab) -> ssba (TCG_BSWAP_OS) + * bswap16_i32(xxab) -> xaba + */ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags) { /* Only one extension flag may be present. */ @@ -1032,22 +1041,29 @@ void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags) TCGv_i32 t0 = tcg_temp_ebb_new_i32(); TCGv_i32 t1 = tcg_temp_ebb_new_i32(); - tcg_gen_shri_i32(t0, arg, 8); + /* arg = xxab (IZ=0) */ + /* = ..ab (IZ=1) */ + tcg_gen_shri_i32(t0, arg, 8); /* t0 = .xxa (IZ=0) */ + /* = ...a (IZ=1) */ if (!(flags & TCG_BSWAP_IZ)) { - tcg_gen_ext8u_i32(t0, t0); + tcg_gen_ext8u_i32(t0, t0); /* t0 = ...a (IZ=0) */ } if (flags & TCG_BSWAP_OS) { - tcg_gen_shli_i32(t1, arg, 24); - tcg_gen_sari_i32(t1, t1, 16); + tcg_gen_shli_i32(t1, arg, 24); /* t1 = b... (OS=1) */ + tcg_gen_sari_i32(t1, t1, 16); /* t1 = ssb. (OS=1) */ } else if (flags & TCG_BSWAP_OZ) { - tcg_gen_ext8u_i32(t1, arg); - tcg_gen_shli_i32(t1, t1, 8); + tcg_gen_ext8u_i32(t1, arg); /* t1 = ...b (OZ=1) */ + tcg_gen_shli_i32(t1, t1, 8); /* t1 = ..b. (OZ=1) */ } else { - tcg_gen_shli_i32(t1, arg, 8); + tcg_gen_shli_i32(t1, arg, 8); /* t1 = xab. (IZ=0) */ + /* = .ab. (IZ=1) */ } - tcg_gen_or_i32(ret, t0, t1); + tcg_gen_or_i32(ret, t0, t1); /* ret = ..ba (OZ=1) */ + /* = ssba (OS=1) */ + /* = .aba (IZ=1) */ + /* = xaba (no flag) */ tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); }