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[209.51.188.17]) by mx.google.com with ESMTPS id y15-20020ac85f4f000000b004109f0847b5si1898756qta.682.2023.08.22.05.42.45 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 22 Aug 2023 05:42:45 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MojuRq3F; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qYQh6-0006KS-5L; Tue, 22 Aug 2023 08:41:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qYQh2-0006Iw-5O for qemu-devel@nongnu.org; Tue, 22 Aug 2023 08:41:08 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qYQgz-0005ZQ-J9 for qemu-devel@nongnu.org; Tue, 22 Aug 2023 08:41:07 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-317c3ac7339so3895586f8f.0 for ; Tue, 22 Aug 2023 05:41:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1692708063; x=1693312863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nsvUqHlFX1jn4aW9Gaw9PjawxbooLIqjbrbXDvQlkNQ=; b=MojuRq3FcpEf1spcBl2fm+knldksxR4XIvwkbCZDoW/kyW6EKK2Aq2JsjcSw4SsnGS 3Ei0IW0w2y3nXhtD47WGgg5chYQMHz8JuUGVok00ftlwd2RA/AzKGgmpVRaQg/nH8mXS sfZJooNcH2Uf0albij0xzSD17WVUA+vGUOhdV3Mqt46lKc5kg2Vw+4bFsj3X97Z2qjG6 TuNu0Tr4geaYFMjoFsUbDSuQtxinxoYM0SpGzzAUoNC1n0yHJAUcPw+p4rGp0Fr722YQ DKMj+PXIbDc73wqMsAKWaCugRD0i/UjJZ32GkP6q0VWfpew4ujfPWS5Wl/NR9FDe3WVr 2GTA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692708063; x=1693312863; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nsvUqHlFX1jn4aW9Gaw9PjawxbooLIqjbrbXDvQlkNQ=; b=Y8fUrRswKqLYN6il18in6zj0zT30GnwGpBGC204whsDurlVKQ9Oly6X51+rbUVVrd/ sRtUci/XUL8pLsU0ipbnJ0vo7Ds30aZQ0qp/6HX4jYho9+10TBJxw6HA3BPWcAmuOddy pyVUi+fASUPELQWj4F2dRAfrRaDE02uOrcASfbH8tFbVhCGp3CDnkG38511nMKXlbmgD vjWAVNWwhM/E38xq3Fg5BOhrHlXpX1Q5pJ/g7JAkZb0YQYn+Nqu6wniTs5RoMhRRWqGp 1xC6ZahYUP6jfntGcXJAoTPpcrlIX+2EJM9WzvgLl6WEVJOugx3mBPijSn9Uah4P9Gii JHzA== X-Gm-Message-State: AOJu0Yy2pwBH6QGP2dKpAXIph4x8hytexzTnfo/zisuPGbDnxUBo+wz7 lk0B/xeZi9a2iwJAnLQeBN6RDfz9bbrsLFCQR2/5Rw== X-Received: by 2002:adf:f70c:0:b0:317:5af3:caa4 with SMTP id r12-20020adff70c000000b003175af3caa4mr7256713wrp.38.1692708063580; Tue, 22 Aug 2023 05:41:03 -0700 (PDT) Received: from localhost.localdomain ([37.19.214.4]) by smtp.gmail.com with ESMTPSA id r15-20020a056000014f00b0031ad5a54bedsm15923239wrx.9.2023.08.22.05.41.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 22 Aug 2023 05:41:03 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Song Gao , "Edgar E. Iglesias" , Richard Henderson , Greg Kurz , Aurelien Jarno , Peter Maydell , qemu-ppc@nongnu.org, Daniel Henrique Barboza , Aleksandar Rikalo , Paolo Bonzini , David Gibson , Jiaxun Yang , =?utf-8?q?C=C3=A9dric_Le_Goater?= , Yoshinori Sato , Nicholas Piggin , Xiaojuan Yang , qemu-arm@nongnu.org Subject: [PATCH 02/12] target/arm: Use generic hrev32_i32() in ARM REV16 and VREV16 opcodes Date: Tue, 22 Aug 2023 14:40:32 +0200 Message-ID: <20230822124042.54739-3-philmd@linaro.org> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230822124042.54739-1-philmd@linaro.org> References: <20230822124042.54739-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate-a32.h | 1 - target/arm/tcg/translate-neon.c | 2 +- target/arm/tcg/translate.c | 14 +------------- 3 files changed, 2 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-a32.h b/target/arm/tcg/translate-a32.h index 0c8f408eea..6cc02c83b9 100644 --- a/target/arm/tcg/translate-a32.h +++ b/target/arm/tcg/translate-a32.h @@ -45,7 +45,6 @@ void gen_lookup_tb(DisasContext *s); long vfp_reg_offset(bool dp, unsigned reg); long neon_full_reg_offset(unsigned reg); long neon_element_offset(int reg, int element, MemOp memop); -void gen_rev16(TCGv_i32 dest, TCGv_i32 var); void clear_eci_state(DisasContext *s); bool mve_eci_check(DisasContext *s); void mve_update_eci(DisasContext *s); diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 0e59b03ff9..9489dc0b3e 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -3528,7 +3528,7 @@ static bool trans_VREV16(DisasContext *s, arg_2misc *a) if (a->size != 0) { return false; } - return do_2misc(s, a, gen_rev16); + return do_2misc(s, a, tcg_gen_hrev32_i32); } static bool trans_VCLS(DisasContext *s, arg_2misc *a) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 39a42611c6..4ebf04f4de 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -416,18 +416,6 @@ static void gen_smul_dual(TCGv_i32 a, TCGv_i32 b) tcg_gen_mov_i32(a, tmp1); } -/* Byteswap each halfword. */ -void gen_rev16(TCGv_i32 dest, TCGv_i32 var) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - TCGv_i32 mask = tcg_constant_i32(0x00ff00ff); - tcg_gen_shri_i32(tmp, var, 8); - tcg_gen_and_i32(tmp, tmp, mask); - tcg_gen_and_i32(var, var, mask); - tcg_gen_shli_i32(var, var, 8); - tcg_gen_or_i32(dest, var, tmp); -} - /* Byteswap low halfword and sign extend. */ static void gen_revsh(TCGv_i32 dest, TCGv_i32 var) { @@ -7578,7 +7566,7 @@ static bool trans_REV16(DisasContext *s, arg_rr *a) if (!ENABLE_ARCH_6) { return false; } - return op_rr(s, a, gen_rev16); + return op_rr(s, a, tcg_gen_hrev32_i32); } static bool trans_REVSH(DisasContext *s, arg_rr *a)