| Message ID | 20230822093712.38922-5-philmd@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | tcg: Document *swap/deposit helpers | expand |
On 8/22/23 02:37, Philippe Mathieu-Daudé wrote: > Document hswap_i32() and hswap_i64(), added in commit > 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}"). > > Signed-off-by: Philippe Mathieu-Daudé<philmd@linaro.org> > --- > docs/devel/tcg-ops.rst | 4 ++++ > tcg/tcg-op.c | 26 +++++++++++++++++++------- > 2 files changed, 23 insertions(+), 7 deletions(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On 8/22/23 02:37, Philippe Mathieu-Daudé wrote: > Document hswap_i32() and hswap_i64(), added in commit > 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}"). > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > docs/devel/tcg-ops.rst | 4 ++++ > tcg/tcg-op.c | 26 +++++++++++++++++++------- > 2 files changed, 23 insertions(+), 7 deletions(-) > > diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst > index 6a166c5665..d9364effd2 100644 > --- a/docs/devel/tcg-ops.rst > +++ b/docs/devel/tcg-ops.rst > @@ -486,6 +486,10 @@ Misc > into 32-bit output *t0*. Depending on the host, this may be a simple shift, > or may require additional canonicalization. > > + * - hswap_i32/i64 *t0*, *t1* > + > + - | Swap 16-bit halfwords within a 32/64-bit value. hswap is not a tcg opcode, so this is incorrect. This falls into the part of TCG that Peter has mentioned many times: we have opcode documentation, but no separate translator front end documentation. r~
diff --git a/docs/devel/tcg-ops.rst b/docs/devel/tcg-ops.rst index 6a166c5665..d9364effd2 100644 --- a/docs/devel/tcg-ops.rst +++ b/docs/devel/tcg-ops.rst @@ -486,6 +486,10 @@ Misc into 32-bit output *t0*. Depending on the host, this may be a simple shift, or may require additional canonicalization. + * - hswap_i32/i64 *t0*, *t1* + + - | Swap 16-bit halfwords within a 32/64-bit value. + Conditional moves ----------------- diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index f4fe13e040..bb64326a1a 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -1091,6 +1091,11 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg) } } +/* + * hswap_i32: Swap 16-bit halfwords within a 32-bit value. + * + * Byte pattern: hswap_i32(abcd) -> cdab + */ void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg) { /* Swapping 2 16-bit elements is a rotate. */ @@ -1878,19 +1883,26 @@ void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg) } } +/* + * hswap_i64: Swap 16-bit halfwords within a 64-bit value. + * + * See hswap64() in include/qemu/bitops.h + * + * Byte pattern: hswap_i64(abcdefgh) -> ghefcdab + */ void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg) { uint64_t m = 0x0000ffff0000ffffull; TCGv_i64 t0 = tcg_temp_ebb_new_i64(); TCGv_i64 t1 = tcg_temp_ebb_new_i64(); - /* See include/qemu/bitops.h, hswap64. */ - tcg_gen_rotli_i64(t1, arg, 32); - tcg_gen_andi_i64(t0, t1, m); - tcg_gen_shli_i64(t0, t0, 16); - tcg_gen_shri_i64(t1, t1, 16); - tcg_gen_andi_i64(t1, t1, m); - tcg_gen_or_i64(ret, t0, t1); + /* arg = abcdefgh */ + tcg_gen_rotli_i64(t1, arg, 32); /* t1 = efghabcd */ + tcg_gen_andi_i64(t0, t1, m); /* t0 = ..gh..cd */ + tcg_gen_shli_i64(t0, t0, 16); /* t0 = gh..cd.. */ + tcg_gen_shri_i64(t1, t1, 16); /* t1 = ..efghab */ + tcg_gen_andi_i64(t1, t1, m); /* t1 = ..ef..ab */ + tcg_gen_or_i64(ret, t0, t1); /* ret = ghefcdab */ tcg_temp_free_i64(t0); tcg_temp_free_i64(t1);
Document hswap_i32() and hswap_i64(), added in commit 46be8425ff ("tcg: Implement tcg_gen_{h,w}swap_{i32,i64}"). Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- docs/devel/tcg-ops.rst | 4 ++++ tcg/tcg-op.c | 26 +++++++++++++++++++------- 2 files changed, 23 insertions(+), 7 deletions(-)