[v2,13/23] tcg/arm: Implement negsetcond_i32

Message ID	20230818221327.150194-14-richard.henderson@linaro.org
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Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: Peter Maydell <peter.maydell@linaro.org> Subject: [PATCH v2 13/23] tcg/arm: Implement negsetcond_i32 Date: Fri, 18 Aug 2023 15:13:17 -0700 Message-Id: <20230818221327.150194-14-richard.henderson@linaro.org> In-Reply-To: <20230818221327.150194-1-richard.henderson@linaro.org> References: <20230818221327.150194-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	tcg: Introduce negsetcond opcodes \| expand [v2,00/23] tcg: Introduce negsetcond opcodes [v2,01/23] tcg: Introduce negsetcond opcodes [v2,02/23] tcg: Use tcg_gen_negsetcond_* [v2,03/23] target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero [v2,04/23] target/arm: Use tcg_gen_negsetcond_* [v2,05/23] target/m68k: Use tcg_gen_negsetcond_* [v2,06/23] target/openrisc: Use tcg_gen_negsetcond_* [v2,07/23] target/ppc: Use tcg_gen_negsetcond_* [v2,08/23] target/sparc: Use tcg_gen_movcond_i64 in gen_edge [v2,09/23] target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl [v2,10/23] tcg/ppc: Implement negsetcond_* [v2,11/23] tcg/ppc: Use the Set Boolean Extension [v2,12/23] tcg/aarch64: Implement negsetcond_* [v2,13/23] tcg/arm: Implement negsetcond_i32 [v2,14/23] tcg/riscv: Implement negsetcond_* [v2,15/23] tcg/s390x: Implement negsetcond_* [v2,16/23] tcg/sparc64: Implement negsetcond_* [v2,17/23] tcg/i386: Merge tcg_out_brcond{32,64} [v2,18/23] tcg/i386: Merge tcg_out_setcond{32,64} [v2,19/23] tcg/i386: Merge tcg_out_movcond{32,64} [v2,20/23] tcg/i386: Use CMP+SBB in tcg_out_setcond [v2,21/23] tcg/i386: Clear dest first in tcg_out_setcond if possible [v2,22/23] tcg/i386: Use shift in tcg_out_setcond [v2,23/23] tcg/i386: Implement negsetcond_*

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20230818221327.150194-14-richard.henderson@linaro.org

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Cc: Peter Maydell <peter.maydell@linaro.org>
Subject: [PATCH v2 13/23] tcg/arm: Implement negsetcond_i32
Date: Fri, 18 Aug 2023 15:13:17 -0700
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Series

tcg: Introduce negsetcond opcodes | expand

Commit Message

Richard Henderson Aug. 18, 2023, 10:13 p.m. UTC

Trivial, as we simply need to load a different constant
in the conditional move.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/arm/tcg-target.h     | 2 +-
 tcg/arm/tcg-target.c.inc | 9 +++++++++
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h
index b076d033a9..b064bbda9f 100644
--- a/tcg/arm/tcg-target.h
+++ b/tcg/arm/tcg-target.h
@@ -122,7 +122,7 @@  extern bool use_neon_instructions;
 #define TCG_TARGET_HAS_mulsh_i32        0
 #define TCG_TARGET_HAS_div_i32          use_idiv_instructions
 #define TCG_TARGET_HAS_rem_i32          0
-#define TCG_TARGET_HAS_negsetcond_i32   0
+#define TCG_TARGET_HAS_negsetcond_i32   1
 #define TCG_TARGET_HAS_qemu_st8_i32     0
 
 #define TCG_TARGET_HAS_qemu_ldst_i128   0
diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
index 83e286088f..162df38c73 100644
--- a/tcg/arm/tcg-target.c.inc
+++ b/tcg/arm/tcg-target.c.inc
@@ -1975,6 +1975,14 @@  static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
                         ARITH_MOV, args[0], 0, 0);
         break;
+    case INDEX_op_negsetcond_i32:
+        tcg_out_dat_rIN(s, COND_AL, ARITH_CMP, ARITH_CMN, 0,
+                        args[1], args[2], const_args[2]);
+        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[args[3]],
+                        ARITH_MVN, args[0], 0, 0);
+        tcg_out_dat_imm(s, tcg_cond_to_arm_cond[tcg_invert_cond(args[3])],
+                        ARITH_MOV, args[0], 0, 0);
+        break;
 
     case INDEX_op_brcond2_i32:
         c = tcg_out_cmp2(s, args, const_args);
@@ -2112,6 +2120,7 @@  static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
     case INDEX_op_add_i32:
     case INDEX_op_sub_i32:
     case INDEX_op_setcond_i32:
+    case INDEX_op_negsetcond_i32:
         return C_O1_I2(r, r, rIN);
 
     case INDEX_op_and_i32:

[v2,13/23] tcg/arm: Implement negsetcond_i32

Commit Message

Patch