From patchwork Tue Aug 8 03:11:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 711569 Delivered-To: patch@linaro.org Received: by 2002:a05:6359:d30:b0:129:c516:61db with SMTP id gp48csp1916679rwb; Mon, 7 Aug 2023 20:18:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFMeYmeO1VEH47FQ8b0/oluotwVvdv9Nfw2necQxiPlChQZWWzF1n6lT2nDgn5dm0OLt5PL X-Received: by 2002:a0c:b40d:0:b0:63d:43aa:e076 with SMTP id u13-20020a0cb40d000000b0063d43aae076mr10368551qve.1.1691464693656; Mon, 07 Aug 2023 20:18:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1691464693; cv=none; d=google.com; s=arc-20160816; b=PmTTME2lIGuvT+8qMHR0JIq5HOZAIr5tlATLKLDl8GHElIF0dh/8gvZxZ5tLYF509B 2DRAHOBgW8tpQEwqfzKLpWP1JmKMhO/pwsmU4rzEtJT8aYk/GvYYVJMJ45OdfP79HnZv qPO8T9twdl1Lip1KzykItNKI1hvKmNTCsx0tH87g0udAvKpbn2oMKqU8OOXLqq0bYu/E ayKFv45cBOcHjN6NgPhqBPnWoIPrnHe97O9sIyALDshcWuY0STZ5so1sP2mM40Do48sU lx0wrQQgn2gFRoGtL6yAaVkPvysLuDLxlACNb+TT9wUruagHtPKGHQW/FB3uQ7O4FUxL 5E7w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HftGyFuliXonCmDTfSQ595T2noxt1RPBvVTS1fEpJE4=; fh=hqs26moy805PsHbwd88lUczy2QdlfF59ojSMxj/DeWg=; b=hVeutMXnO3NdF8/4v/IArCumFgnDstOmmiVFMPFduWTcuOurLdNJleYcfW8cItFnpo GZ0DMY6XOcg1bEk/KEQjelmCt6mArNsye1Z+CpnUGJP26zKV00hHRNyLNeh/7dyed/g2 RFAD5h8mIS7fXQKxcZCBRj1Q7aysJ1QIRu4Lf7LNzVpHJ+kUOLTzmo+q11NLjiAV9XRu Kp9DaygujgMQNzziz5mjvuseB/k16CAHd0bbBNiUdxq0yOOJbJxj76UQVrNFJCVF+RIy tuCmpz36tzCqIojK3YNPAUElQZ5a7zxQURb/L2sCq7rhcfGMdlXpWpFZj71Ur2maoUfy AznQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qyZ4ShXL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k6-20020a0cabc6000000b0060f7b695034si5477571qvb.426.2023.08.07.20.18.13 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 07 Aug 2023 20:18:13 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qyZ4ShXL; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qTD8Z-0000Ew-QK; Mon, 07 Aug 2023 23:11:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qTD8X-0000Bo-Uz for qemu-devel@nongnu.org; Mon, 07 Aug 2023 23:11:57 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qTD8P-000091-Nm for qemu-devel@nongnu.org; Mon, 07 Aug 2023 23:11:57 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-563df158ecaso3806030a12.0 for ; Mon, 07 Aug 2023 20:11:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1691464308; x=1692069108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HftGyFuliXonCmDTfSQ595T2noxt1RPBvVTS1fEpJE4=; b=qyZ4ShXL/IiCMFN/uaOF8PrML7SdB9xDL81Mx3A6DQq5Sx0QJhmTdhXDeoHZZKwh5+ oKgpoH0rHWQytnAsV4cOFC0pGnSbhSTo4ArfifOsWDtQ1suzW91GdNvlS8VChGCEOZND yTd6jD6fORf70WR3Y0IwbVzYQiscOJnzO6JlzNqdTzcPjEbBBPFaKnyTfuFmp5PH1Rlt kBVS3Ld4ry1eno0TZoplPwsU01L7OwqMyWXluCS871Gfy898tKQ0aK8MVbi9FwSaVQMA 3dFBekgfS9/GkgvxCvUWn4y/A9B7jRRxE43qNo/lnttA8ztmf2TX4jBP6/5ITweMdnS+ +C7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1691464308; x=1692069108; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HftGyFuliXonCmDTfSQ595T2noxt1RPBvVTS1fEpJE4=; b=c0Wkzaf1rbZjJmwcAzAKQJBRpAZT49dY171ze3i6VdEjZ5lvHSJg/TBJ7wtp7aDcZu c/WrHb6SxmlWKI1r40QvKJ6jBo6qf2u9Ia3JOki+M8uCu8ZIB69HogrMLS1D/o0KO/cS cfWTIdRjLIZiONnZ+xWxi44TFMU8UmWSh4iMwc9r4vz3+DyIP4Xujv0n2K7eFjMBCkRX SA0ZxaZFxj4zyqSBdSrlm0pY6FNYmjQPILGPp/ojrTKTRnOCYPgtcn/V5uYFNkv+u6hc o4ztDLLhdb52SJ7KZ8ihAaBSYKtPfniW+lC+1YJ054r1tWOMklQfjwow2sIjCnHeQAhw ItUw== X-Gm-Message-State: AOJu0Yxcnm86x0LYEGNFureRD+4NvXgofpDmxJyjp7IRBqIdCCHQCmd9 yr1vdFRHkviijNPmey2RZCy6NpqJuX+14/sSMeE= X-Received: by 2002:a05:6a20:9154:b0:13e:8ce5:bed4 with SMTP id x20-20020a056a20915400b0013e8ce5bed4mr14442332pzc.7.1691464308275; Mon, 07 Aug 2023 20:11:48 -0700 (PDT) Received: from stoup.. ([2602:47:d490:6901:e306:567a:e0a1:341]) by smtp.gmail.com with ESMTPSA id g64-20020a636b43000000b0055bf96b11d9sm5639087pgc.89.2023.08.07.20.11.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Aug 2023 20:11:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-ppc@nongnu.org, qemu-riscv@nongnu.org, qemu-s390x@nongnu.org Subject: [PATCH 04/24] target/arm: Use tcg_gen_negsetcond_* Date: Mon, 7 Aug 2023 20:11:23 -0700 Message-Id: <20230808031143.50925-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230808031143.50925-1-richard.henderson@linaro.org> References: <20230808031143.50925-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, SUSPICIOUS_RECIPS=2.51 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/tcg/translate-a64.c | 22 +++++++++------------- target/arm/tcg/translate.c | 12 ++++-------- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 5fa1257d32..ac16593699 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -4935,9 +4935,12 @@ static void disas_cond_select(DisasContext *s, uint32_t insn) if (rn == 31 && rm == 31 && (else_inc ^ else_inv)) { /* CSET & CSETM. */ - tcg_gen_setcond_i64(tcg_invert_cond(c.cond), tcg_rd, c.value, zero); if (else_inv) { - tcg_gen_neg_i64(tcg_rd, tcg_rd); + tcg_gen_negsetcond_i64(tcg_invert_cond(c.cond), + tcg_rd, c.value, zero); + } else { + tcg_gen_setcond_i64(tcg_invert_cond(c.cond), + tcg_rd, c.value, zero); } } else { TCGv_i64 t_true = cpu_reg(s, rn); @@ -8670,13 +8673,10 @@ static void handle_3same_64(DisasContext *s, int opcode, bool u, } break; case 0x6: /* CMGT, CMHI */ - /* 64 bit integer comparison, result = test ? (2^64 - 1) : 0. - * We implement this using setcond (test) and then negating. - */ cond = u ? TCG_COND_GTU : TCG_COND_GT; do_cmop: - tcg_gen_setcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); - tcg_gen_neg_i64(tcg_rd, tcg_rd); + /* 64 bit integer comparison, result = test ? -1 : 0. */ + tcg_gen_negsetcond_i64(cond, tcg_rd, tcg_rn, tcg_rm); break; case 0x7: /* CMGE, CMHS */ cond = u ? TCG_COND_GEU : TCG_COND_GE; @@ -9265,14 +9265,10 @@ static void handle_2misc_64(DisasContext *s, int opcode, bool u, } break; case 0xa: /* CMLT */ - /* 64 bit integer comparison against zero, result is - * test ? (2^64 - 1) : 0. We implement via setcond(!test) and - * subtracting 1. - */ + /* 64 bit integer comparison against zero, result is test ? 1 : 0. */ cond = TCG_COND_LT; do_cmop: - tcg_gen_setcondi_i64(cond, tcg_rd, tcg_rn, 0); - tcg_gen_neg_i64(tcg_rd, tcg_rd); + tcg_gen_negsetcond_i64(cond, tcg_rd, tcg_rn, tcg_constant_i64(0)); break; case 0x8: /* CMGT, CMGE */ cond = u ? TCG_COND_GE : TCG_COND_GT; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index b71ac2d0d5..31d3130e4c 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -2946,13 +2946,11 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, #define GEN_CMP0(NAME, COND) \ static void gen_##NAME##0_i32(TCGv_i32 d, TCGv_i32 a) \ { \ - tcg_gen_setcondi_i32(COND, d, a, 0); \ - tcg_gen_neg_i32(d, d); \ + tcg_gen_negsetcond_i32(COND, d, a, tcg_constant_i32(0)); \ } \ static void gen_##NAME##0_i64(TCGv_i64 d, TCGv_i64 a) \ { \ - tcg_gen_setcondi_i64(COND, d, a, 0); \ - tcg_gen_neg_i64(d, d); \ + tcg_gen_negsetcond_i64(COND, d, a, tcg_constant_i64(0)); \ } \ static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \ { \ @@ -3863,15 +3861,13 @@ void gen_gvec_mls(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs, static void gen_cmtst_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) { tcg_gen_and_i32(d, a, b); - tcg_gen_setcondi_i32(TCG_COND_NE, d, d, 0); - tcg_gen_neg_i32(d, d); + tcg_gen_negsetcond_i32(TCG_COND_NE, d, d, tcg_constant_i32(0)); } void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { tcg_gen_and_i64(d, a, b); - tcg_gen_setcondi_i64(TCG_COND_NE, d, d, 0); - tcg_gen_neg_i64(d, d); + tcg_gen_negsetcond_i64(TCG_COND_NE, d, d, tcg_constant_i64(0)); } static void gen_cmtst_vec(unsigned vece, TCGv_vec d, TCGv_vec a, TCGv_vec b)