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[209.51.188.17]) by mx.google.com with ESMTPS id f10-20020a05620a20ca00b00765a635ade2si11892566qka.309.2023.07.04.07.52.15 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:52:15 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=meF2wC2V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNj-0007KV-3O; Tue, 04 Jul 2023 10:51:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhNg-0007BK-Me for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:53 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhNd-0003Jd-Ia for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:50 -0400 Received: by mail-wm1-x32b.google.com with SMTP id 5b1f17b1804b1-3fbc54cab6fso49730015e9.0 for ; Tue, 04 Jul 2023 07:51:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482308; x=1691074308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9WVD5h3S/wXD+ivo8E/ihZP+IS9902/QRoD0axxhHzM=; b=meF2wC2VGEmyjNWlAdgFdYbc/KsIi6e87i2G7rYUKZA02OC1xtL6VzlJdBjmU4xALY JhB1juM7FNR9uyxIVefP5e4u3qOo9EwtmrXLy94BFwZ3mwfM1Oy6gtfGQzwdNP9jPp39 mufaUN9vOWXu/LdeNf6a4wVbsBsxL8zGYXWJNi4P9GkIPmY/QhrhBAWA/USlXtxCRiVx 9WsECgux3cYEeb9f1HqWfHQcBiQlBRl38RLim/donORD95eyAt5C8Igrt5X7P4fsFw41 aprUMYpHBiW6ax7zdBkXWWry4jTGQFTvgx/RZ3xs1hBS1hv+eG7gvWdBc8ReEQ07tDQw 8iWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482308; x=1691074308; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9WVD5h3S/wXD+ivo8E/ihZP+IS9902/QRoD0axxhHzM=; b=AwbRcRD2Zgpe8oHAGbst4Y4XB3dcA2aEDh72gqccYrRE6bp4VXDvBy8imGQEqJei1j 76zninP5PInVnAseWKz/8Y7kIgmo7FVxqJbIc5j8hRt+ZhCWrLkCRgBZ5uW4z+Kigq7/ bDm0M3f5/6DJmBy81tgNWkOl7w1RGRX4FUGcvp7gnvZvafuMklhxXSZFMLVZyl6ut3Ed sukTSzV8ChHaV0A2xdgz9c5PwOPVPUnWcrsWeakSBbED10a4zKZ2cGqYzZLYweLCiLtF BmZrtVdmNE5ta3tpBUW6vxCeWyhgUlhh+HVptbZtiL85cXdFwahSJb9ObrDfqhxg/P8/ oaIw== X-Gm-Message-State: AC+VfDyiAwsSmu4fc1P/w4luEBujOx/F/CLuq/sW+pdoiqOVlUTx4DcU ZNEHFXhSUNoYkeGT9eIXQzzWjnltH3v/bSOrlHM= X-Received: by 2002:a7b:cbd0:0:b0:3fa:8db4:91ec with SMTP id n16-20020a7bcbd0000000b003fa8db491ecmr10380467wmi.10.1688482308089; Tue, 04 Jul 2023 07:51:48 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id o11-20020a05600c378b00b003fa95f328afsm25654281wmr.29.2023.07.04.07.51.47 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:47 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 18/19] hw/timer/arm_timer: Map ARM_TIMER MMIO regions into IntegratorPIT Date: Tue, 4 Jul 2023 16:50:11 +0200 Message-Id: <20230704145012.49870-19-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of manually forwarding MMIO accesses to each ARM_TIMER, let have the generic memory code dispatch that for us. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 43 ++++--------------------------------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 8207723ab5..7b455aff4d 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -393,6 +393,7 @@ static void sp804_class_init(ObjectClass *klass, void *data) } /* Integrator/CP timer module. */ +/* ??? Don't know the PrimeCell ID for this device. */ #define TYPE_INTEGRATOR_PIT "integrator_pit" OBJECT_DECLARE_SIMPLE_TYPE(IntegratorPIT, INTEGRATOR_PIT) @@ -405,43 +406,6 @@ struct IntegratorPIT { qemu_irq irq[3]; }; -static uint64_t icp_pit_read(void *opaque, hwaddr offset, - unsigned size) -{ - IntegratorPIT *s = opaque; - int n; - - /* ??? Don't know the PrimeCell ID for this device. */ - n = offset >> 8; - if (n > 2) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); - return 0; - } - - return arm_timer_read(&s->timer[n], offset & 0xff, size); -} - -static void icp_pit_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - IntegratorPIT *s = opaque; - int n; - - n = offset >> 8; - if (n > 2) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); - return; - } - - arm_timer_write(&s->timer[n], offset & 0xff, value, size); -} - -static const MemoryRegionOps icp_pit_ops = { - .read = icp_pit_read, - .write = icp_pit_write, - .endianness = DEVICE_NATIVE_ENDIAN, -}; - static void icp_pit_fwd_irq(void *opaque, int n, int level) { IntegratorPIT *s = opaque; @@ -469,8 +433,7 @@ static void icp_pit_init(Object *obj) sysbus_init_irq(dev, &s->irq[i]); } - memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, - "icp_pit", 0x1000); + memory_region_init(&s->iomem, obj, "icp_pit", 0x1000); sysbus_init_mmio(dev, &s->iomem); /* This device has no state to save/restore. The component timers will save themselves. */ @@ -487,6 +450,8 @@ static void icp_pit_realize(DeviceState *dev, Error **errp) return; } sysbus_connect_irq(tmr, 0, qdev_get_gpio_in_named(dev, "timer-in", i)); + memory_region_add_subregion(&s->iomem, 0x100 * i, + sysbus_mmio_get_region(tmr, 0)); } }