From patchwork Tue Jul 4 13:06:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698935 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2266482wrs; Tue, 4 Jul 2023 06:07:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4iraROYXG21spk0Rx2jwMh9CQLKll23JCvmFKYg2TY3ut0nvsoEq18xE+mRrJ44hfQ7znb X-Received: by 2002:a05:622a:113:b0:3ff:33d6:da9f with SMTP id u19-20020a05622a011300b003ff33d6da9fmr15528299qtw.49.1688476068682; Tue, 04 Jul 2023 06:07:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688476068; cv=none; d=google.com; s=arc-20160816; b=KSGPCt7MrmUhaTNem1Fbo2toUxCgFA6sfBchQ0T1XheLZWGLGCqPLcsSPuyniSmuTJ Q/f4crJTAecPCxop8lQS21y+CNguDPoM1V5qO3MFJr2QwQ7NqfrvrwZp88ss2lhXaxnw mxggA4VB9sIJq6CLwR03K1IZl7McPZjG+OBDNzpTcfZUztvBFhb3c6O5UoLcAZ5Q7Ocg 0Qy+avM0lmYuZjzAmpcThDy0UOWDydgKeeeIjeZrbF2xGrKKpBXl4GKDXD2x57FKtfCu s9Iv8j9WjtHCHOBl+ccnC6s/n4MVVkWIaykcYfNKA1nbfjX0yJ8CPzxKAXTcwMyOsV/I 2Jbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=o63W7D3dZ+IsTd+CBM4Ktiq6kGzSxYbY5hWwGmlhVKI=; fh=H2AmuqulvQE+T5zu97MCEUC3z9wF9NssS7895NhR/+c=; b=b/DPAQ71cE4eAiYcjYdWqBE8vlQOJBxwqGiWcRAlRBidOJCDncmrU/b6tksFEAJkae 9beuQ8JSop76gxQUKfE53lXitRe5YzCyGS4jmgh5YCgQkGvW2UHwY2FhLciBUTQyRyZ9 WmCHMehDJhdCuhB+rbsbCUlPLksfCzNYh7h0frXkEJR2fSI/gpGErg72UMSlRdrh/ztK w1KkqOUs1f5XHaT4bTA3c0jfD/dnB7WpOq+8ZOhUDEAvU6gulGhKI+ZGrgblZinfvlIy PQu/o47UtRcdcDg0pbdnLl7r2bI315jzWIOHKukvzOz3kvH5+JT4toSEXgmOZbMAG9Yv 1x8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="o/7LlAin"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 10-20020ac84e8a000000b0040333b2be18si7664332qtp.154.2023.07.04.06.07.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 06:07:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="o/7LlAin"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGfk8-0001S2-GQ; Tue, 04 Jul 2023 09:06:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGfk6-0001Qw-M5 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 09:06:54 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGfk4-0003UR-PJ for qemu-devel@nongnu.org; Tue, 04 Jul 2023 09:06:54 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-3110ab7110aso6341106f8f.3 for ; Tue, 04 Jul 2023 06:06:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688476011; x=1691068011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=o63W7D3dZ+IsTd+CBM4Ktiq6kGzSxYbY5hWwGmlhVKI=; b=o/7LlAin+0uYGz9C3AJ7WPZGIXtjSpAzH/8HH/LAwM1WX1i5PviJvpWlvnP3DTGR97 Smlm5NYu6jGCyEW4mVMcyq+B1W9v93SidGGnJrq5SX9SxR+R71u40KlCcnzFjyMC7Kni PPW2A5DWNPx5dWaxXJFcpldgxa5kuM8nvDxisIDQvnzIZBiYjYbrzezW7zhTZUl7XbJa WD0qq8yFHXI1oxtEGl7I17mKy3ZriRgGR+azn3ClGPxFTbYv4QbwstWDjFRNRNivC/MO il3w3JyT5qfLtwbDeMuqKpl3so+xLVqmfZacU2mSEyFoMwLMzadggjIm69+NAtUmRA24 Oktw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688476011; x=1691068011; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=o63W7D3dZ+IsTd+CBM4Ktiq6kGzSxYbY5hWwGmlhVKI=; b=OcdZvtGHnsbGXvf23tTOPoQEP7JxioCXewELl4R4qQQuHEtaR0w+DM4MpfhSUFFPOq hT3Bw/KhWL+FvnssrIELDElmEj2fztjqlbxJN2ASZkbNcvdAeFEeDpMrnvrK1FVOxqpj knjfzQrwNLXbXBXYkqsYCQCX4tULi1ggkYuZcTcAveDMxDSNtCLKW4iYnid0xiM02q6F h+OQ8sJAZzfZqIfjQRclcMfqCfIhuKlUZg9ZWpy4G8bc5CvqekBqcggPXvaVC8inrFjZ 2RLwBHU9cnuPjIxArmpvGqiZ1k0cs5o7Tzo9m43AQYNoM4nZAHNxlVehLBYYoRx6xOed AQpQ== X-Gm-Message-State: ABy/qLbWMgwPDqFJOve46G824D/IcydEeJWEKdG6A/42u+NBdFQn4k3W EggWIf5bnFyyh7PT9aLBPfg8nA== X-Received: by 2002:a5d:4445:0:b0:314:3a3d:5d1f with SMTP id x5-20020a5d4445000000b003143a3d5d1fmr4353699wrr.19.1688476010311; Tue, 04 Jul 2023 06:06:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id a10-20020adfeeca000000b00314103d6daesm15834737wrp.47.2023.07.04.06.06.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 06:06:50 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/2] target/arm: Suppress more TCG unimplemented features in ID registers Date: Tue, 4 Jul 2023 14:06:46 +0100 Message-Id: <20230704130647.2842917-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704130647.2842917-1-peter.maydell@linaro.org> References: <20230704130647.2842917-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We already squash the ID register field for FEAT_SPE (the Statistical Profiling Extension) because TCG does not implement it and if we advertise it to the guest the guest will crash trying to look at non-existent system registers. Do the same for some other features which a real hardware Neoverse-V1 implements but which TCG doesn't: * FEAT_TRF (Self-hosted Trace Extension) * Trace Macrocell system register access * Memory mapped trace * FEAT_AMU (Activity Monitors Extension) * FEAT_MPAM (Memory Partitioning and Monitoring Extension) * FEAT_NV (Nested Virtualization) Most of these, like FEAT_SPE, are "introspection/trace" type features which QEMU is unlikely to ever implement. The odd-one-out here is FEAT_NV -- we could implement that and at some point we probably will. Signed-off-by: Peter Maydell Reviewed-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/cpu.c | 33 +++++++++++++++++++++++++++++---- 1 file changed, 29 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1e77698ba2..7eb7e909097 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2048,13 +2048,38 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) if (tcg_enabled()) { /* - * Don't report the Statistical Profiling Extension in the ID - * registers, because TCG doesn't implement it yet (not even a - * minimal stub version) and guests will fall over when they - * try to access the non-existent system registers for it. + * Don't report some architectural features in the ID registers + * where TCG does not yet implement it (not even a minimal + * stub version). This avoids guests falling over when they + * try to access the non-existent system registers for them. */ + /* FEAT_SPE (Statistical Profiling Extension) */ cpu->isar.id_aa64dfr0 = FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, PMSVER, 0); + /* FEAT_TRF (Self-hosted Trace Extension) */ + cpu->isar.id_aa64dfr0 = + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEFILT, 0); + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, TRACEFILT, 0); + /* Trace Macrocell system register access */ + cpu->isar.id_aa64dfr0 = + FIELD_DP64(cpu->isar.id_aa64dfr0, ID_AA64DFR0, TRACEVER, 0); + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPTRC, 0); + /* Memory mapped trace */ + cpu->isar.id_dfr0 = + FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, MMAPTRC, 0); + /* FEAT_AMU (Activity Monitors Extension) */ + cpu->isar.id_aa64pfr0 = + FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, AMU, 0); + cpu->isar.id_pfr0 = + FIELD_DP32(cpu->isar.id_pfr0, ID_PFR0, AMU, 0); + /* FEAT_MPAM (Memory Partitioning and Monitoring Extension) */ + cpu->isar.id_aa64pfr0 = + FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, MPAM, 0); + /* FEAT_NV (Nested Virtualization) */ + cpu->isar.id_aa64mmfr2 = + FIELD_DP64(cpu->isar.id_aa64mmfr2, ID_AA64MMFR2, NV, 0); } /* MPU can be configured out of a PMSA CPU either by setting has-mpu