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[188.79.232.91]) by smtp.gmail.com with ESMTPSA id t5-20020a05600001c500b00313f7b077fesm18446562wrx.59.2023.07.03.03.05.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 03:05:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, alistair.francis@wdc.com, danielhb413@gmail.com, =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= , =?utf-8?q?Phi?= =?utf-8?q?lippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v4 35/37] crypto: Implement aesdec_IMC with AES_imc_rot Date: Mon, 3 Jul 2023 12:05:18 +0200 Message-Id: <20230703100520.68224-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230703100520.68224-1-richard.henderson@linaro.org> References: <20230703100520.68224-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This method uses one uint32_t * 256 table instead of 4, which means its data cache overhead is less. Acked-by: Daniel P. Berrangé Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- crypto/aes.c | 42 +++++++++++++++++++++--------------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/crypto/aes.c b/crypto/aes.c index 00e16d3f92..d93883eb18 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -1377,39 +1377,39 @@ aesdec_IMC_swap(AESState *r, const AESState *st, bool swap) bool be = HOST_BIG_ENDIAN ^ swap; uint32_t t; - /* Note that AES_imc is encoded for big-endian. */ - t = (AES_imc[st->b[swap_b ^ 0x0]][0] ^ - AES_imc[st->b[swap_b ^ 0x1]][1] ^ - AES_imc[st->b[swap_b ^ 0x2]][2] ^ - AES_imc[st->b[swap_b ^ 0x3]][3]); - if (!be) { + /* Note that AES_imc_rot is encoded for little-endian. */ + t = ( AES_imc_rot[st->b[swap_b ^ 0x0]] ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0x1]], 8) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0x2]], 16) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0x3]], 24)); + if (be) { t = bswap32(t); } r->w[swap_w ^ 0] = t; - t = (AES_imc[st->b[swap_b ^ 0x4]][0] ^ - AES_imc[st->b[swap_b ^ 0x5]][1] ^ - AES_imc[st->b[swap_b ^ 0x6]][2] ^ - AES_imc[st->b[swap_b ^ 0x7]][3]); - if (!be) { + t = ( AES_imc_rot[st->b[swap_b ^ 0x4]] ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0x5]], 8) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0x6]], 16) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0x7]], 24)); + if (be) { t = bswap32(t); } r->w[swap_w ^ 1] = t; - t = (AES_imc[st->b[swap_b ^ 0x8]][0] ^ - AES_imc[st->b[swap_b ^ 0x9]][1] ^ - AES_imc[st->b[swap_b ^ 0xA]][2] ^ - AES_imc[st->b[swap_b ^ 0xB]][3]); - if (!be) { + t = ( AES_imc_rot[st->b[swap_b ^ 0x8]] ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0x9]], 8) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0xA]], 16) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0xB]], 24)); + if (be) { t = bswap32(t); } r->w[swap_w ^ 2] = t; - t = (AES_imc[st->b[swap_b ^ 0xC]][0] ^ - AES_imc[st->b[swap_b ^ 0xD]][1] ^ - AES_imc[st->b[swap_b ^ 0xE]][2] ^ - AES_imc[st->b[swap_b ^ 0xF]][3]); - if (!be) { + t = ( AES_imc_rot[st->b[swap_b ^ 0xC]] ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0xD]], 8) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0xE]], 16) ^ + rol32(AES_imc_rot[st->b[swap_b ^ 0xF]], 24)); + if (be) { t = bswap32(t); } r->w[swap_w ^ 3] = t;