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[188.79.232.91]) by smtp.gmail.com with ESMTPSA id t5-20020a05600001c500b00313f7b077fesm18446562wrx.59.2023.07.03.03.05.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Jul 2023 03:05:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com, eduardo@habkost.net, alistair.francis@wdc.com, danielhb413@gmail.com, =?utf-8?q?Daniel_P_=2E_Berrang=C3=A9?= Subject: [PATCH v4 10/37] crypto: Add aesdec_ISB_ISR_IMC_AK Date: Mon, 3 Jul 2023 12:04:53 +0200 Message-Id: <20230703100520.68224-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230703100520.68224-1-richard.henderson@linaro.org> References: <20230703100520.68224-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add a primitive for InvSubBytes + InvShiftRows + InvMixColumns + AddRoundKey. Acked-by: Daniel P. Berrangé Signed-off-by: Richard Henderson --- host/include/generic/host/crypto/aes-round.h | 3 + include/crypto/aes-round.h | 21 +++++++ crypto/aes.c | 58 ++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/host/include/generic/host/crypto/aes-round.h b/host/include/generic/host/crypto/aes-round.h index 9886e81e50..db8cfe17eb 100644 --- a/host/include/generic/host/crypto/aes-round.h +++ b/host/include/generic/host/crypto/aes-round.h @@ -23,5 +23,8 @@ void aesdec_IMC_accel(AESState *, const AESState *, bool) void aesdec_ISB_ISR_AK_accel(AESState *, const AESState *, const AESState *, bool) QEMU_ERROR("unsupported accel"); +void aesdec_ISB_ISR_IMC_AK_accel(AESState *, const AESState *, + const AESState *, bool) + QEMU_ERROR("unsupported accel"); #endif /* GENERIC_HOST_CRYPTO_AES_ROUND_H */ diff --git a/include/crypto/aes-round.h b/include/crypto/aes-round.h index 03688c8640..9996f1c219 100644 --- a/include/crypto/aes-round.h +++ b/include/crypto/aes-round.h @@ -119,4 +119,25 @@ static inline void aesdec_ISB_ISR_AK(AESState *r, const AESState *st, } } +/* + * Perform InvSubBytes + InvShiftRows + InvMixColumns + AddRoundKey. + */ + +void aesdec_ISB_ISR_IMC_AK_gen(AESState *ret, const AESState *st, + const AESState *rk); +void aesdec_ISB_ISR_IMC_AK_genrev(AESState *ret, const AESState *st, + const AESState *rk); + +static inline void aesdec_ISB_ISR_IMC_AK(AESState *r, const AESState *st, + const AESState *rk, bool be) +{ + if (HAVE_AES_ACCEL) { + aesdec_ISB_ISR_IMC_AK_accel(r, st, rk, be); + } else if (HOST_BIG_ENDIAN == be) { + aesdec_ISB_ISR_IMC_AK_gen(r, st, rk); + } else { + aesdec_ISB_ISR_IMC_AK_genrev(r, st, rk); + } +} + #endif /* CRYPTO_AES_ROUND_H */ diff --git a/crypto/aes.c b/crypto/aes.c index a193d98d54..c2546ef12e 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -1484,6 +1484,64 @@ void aesdec_ISB_ISR_AK_genrev(AESState *r, const AESState *s, const AESState *k) aesdec_ISB_ISR_AK_swap(r, s, k, true); } +/* + * Perform InvSubBytes + InvShiftRows + InvMixColumns + AddRoundKey. + */ +static inline void +aesdec_ISB_ISR_IMC_AK_swap(AESState *r, const AESState *st, + const AESState *rk, bool swap) +{ + int swap_b = swap * 0xf; + int swap_w = swap * 0x3; + bool be = HOST_BIG_ENDIAN ^ swap; + uint32_t w0, w1, w2, w3; + + w0 = (AES_Td0[st->b[swap_b ^ AES_ISH(0x0)]] ^ + AES_Td1[st->b[swap_b ^ AES_ISH(0x1)]] ^ + AES_Td2[st->b[swap_b ^ AES_ISH(0x2)]] ^ + AES_Td3[st->b[swap_b ^ AES_ISH(0x3)]]); + + w1 = (AES_Td0[st->b[swap_b ^ AES_ISH(0x4)]] ^ + AES_Td1[st->b[swap_b ^ AES_ISH(0x5)]] ^ + AES_Td2[st->b[swap_b ^ AES_ISH(0x6)]] ^ + AES_Td3[st->b[swap_b ^ AES_ISH(0x7)]]); + + w2 = (AES_Td0[st->b[swap_b ^ AES_ISH(0x8)]] ^ + AES_Td1[st->b[swap_b ^ AES_ISH(0x9)]] ^ + AES_Td2[st->b[swap_b ^ AES_ISH(0xA)]] ^ + AES_Td3[st->b[swap_b ^ AES_ISH(0xB)]]); + + w3 = (AES_Td0[st->b[swap_b ^ AES_ISH(0xC)]] ^ + AES_Td1[st->b[swap_b ^ AES_ISH(0xD)]] ^ + AES_Td2[st->b[swap_b ^ AES_ISH(0xE)]] ^ + AES_Td3[st->b[swap_b ^ AES_ISH(0xF)]]); + + /* Note that AES_TdX is encoded for big-endian. */ + if (!be) { + w0 = bswap32(w0); + w1 = bswap32(w1); + w2 = bswap32(w2); + w3 = bswap32(w3); + } + + r->w[swap_w ^ 0] = rk->w[swap_w ^ 0] ^ w0; + r->w[swap_w ^ 1] = rk->w[swap_w ^ 1] ^ w1; + r->w[swap_w ^ 2] = rk->w[swap_w ^ 2] ^ w2; + r->w[swap_w ^ 3] = rk->w[swap_w ^ 3] ^ w3; +} + +void aesdec_ISB_ISR_IMC_AK_gen(AESState *r, const AESState *st, + const AESState *rk) +{ + aesdec_ISB_ISR_IMC_AK_swap(r, st, rk, false); +} + +void aesdec_ISB_ISR_IMC_AK_genrev(AESState *r, const AESState *st, + const AESState *rk) +{ + aesdec_ISB_ISR_IMC_AK_swap(r, st, rk, true); +} + /** * Expand the cipher key into the encryption key schedule. */