From patchwork Mon Jun 26 23:19:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 696520 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp3474812wrm; Mon, 26 Jun 2023 16:20:58 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6VOgxLsNy4afSOTjoBtsK7bMppTvzJIEN3550cmU0K7bj+ApkjHhGlxc2xMAs+PvRqu6sY X-Received: by 2002:ac8:4e4d:0:b0:400:9209:67ce with SMTP id e13-20020ac84e4d000000b00400920967cemr9278789qtw.40.1687821658691; Mon, 26 Jun 2023 16:20:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687821658; cv=none; d=google.com; s=arc-20160816; b=rWwYmv6y1AiO549QuDpI3lfn5KetZ+AVL+DNbaxglqAQEJqP2Oq5+SNvm6d6UHSZHx QAQpQuR6ZInoXYqc+B+fw7fpgs+viLdMm5dsHz7HZLyIc+HThFLcLp5j2vO7YcxhGWFn SZ9TYi51yhv7v8bwcXGTgr+Ts5Pyw4VC16WG54Uwpx1rD6kUYNI7l8nOeRjrebFEM8hx Aj/vPXxdkCzl8e8Bq+cAOfrVmN2oYydTup52gM1no1D+hCqMJrfWqhlGO5ridNj+VExp 2K2QwAhb0LPKVIoDOUKEtsq5cQqe5hznt6eYql0ncNJsBhPyLJJbkVQM2WzsOE4cPwXF oIaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9n9ArHz60JzWE1yJqemnhDvR/HZJtedzb/UUiT/wvC8=; fh=Q5PWRR3YGPXeAkQ7IpHJrCtvtZBBd6Ig9aRmT7uxHvE=; b=L3MELBVOU4iiRLrA+41NVwMt6Co+AAZHKvpLc6xGgF1Qot9bs3vFyK09j+Om8hbija Bhx/BIOSXKahnEGu5Cl7f5f2BcX67bgeGBIJ7IuXBnnkJme5LIGBPeDeT3jDOq5bCziH P6BhqmYLhwxZY4xfNOEwTdP6zi8mPtBxrDojrp0+/C4WCKgQNlS/dZs+S5j7qM5i8dic s6NV1zjefV6d0ayF6KGtS7V0tZy3FPNXrUpAf/v5zcZbEZyHty2CAz5fAi8SQwdkumoj XF3B0fJdkbwRej9t9etdBSA81kA6aKI1aeOgEkYKjQC5pdJaAc7SyhTzvqAsJ39LUB6y OF2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bxzSKNJ7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w9-20020ac857c9000000b003f530fda2cdsi883179qta.62.2023.06.26.16.20.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 26 Jun 2023 16:20:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=bxzSKNJ7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qDvVg-0004dY-Io; Mon, 26 Jun 2023 19:20:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qDvVf-0004dB-2H for qemu-devel@nongnu.org; Mon, 26 Jun 2023 19:20:39 -0400 Received: from mail-ej1-x630.google.com ([2a00:1450:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qDvVd-0008Sv-E7 for qemu-devel@nongnu.org; Mon, 26 Jun 2023 19:20:38 -0400 Received: by mail-ej1-x630.google.com with SMTP id a640c23a62f3a-98e1d3be004so292560166b.1 for ; Mon, 26 Jun 2023 16:20:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687821636; x=1690413636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9n9ArHz60JzWE1yJqemnhDvR/HZJtedzb/UUiT/wvC8=; b=bxzSKNJ73QcO7iLvYeLyG0dnR9SiUgtOksbo/GmR2Ym9lThpIqrHxVbGGVKvbSA5GQ Xw5HbE3nOapG4+8j6SNoD/WZXLNoe13LvtFYkNHec0enGQahL2NilnahIfw0Nc0AkdD/ sMGLPM9JlT+LnKA2vURENJe0c82DuW/xiDz5dYA3CU/CExV0E7k3cM0vw9Fg1E8FeOhI kTfR21jy/Cw34CLeD0b91H1Hjux3QJ9bJDygJ88GhgPQPiKyyTAKa7+BTxSl3njPbVWv Axv/D5toJR1VO5+aT2vV6SjpHOB1ZrBhE9oW565pNSREEojW+3tNVzh9PhMEXCYER8EF KT5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687821636; x=1690413636; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9n9ArHz60JzWE1yJqemnhDvR/HZJtedzb/UUiT/wvC8=; b=ba13NMgoMxnTBSql/xGkByUpxtywBO3hFINxdnlbaN7Eb8p4AsL9XDRLyYfXhB5AvU K7FTrQIJYeNmNXl0KF8nltQHtZCkBOmhusBsS/8/6lmjQp3Q07MRxn7QEe9KmbhqwWsO uO/yvTN6goq3wZnJsOnSzUjaghGbjKVeFdLHK10PcFrid5QVX2TCaywE0qBiggLBHgbQ lMTtihklNusYDzkwDsimnKkcz458NMzVYwS8qqwH1+OKBB1atnt9buzbmJk2puG+age2 Oe/vK3NS4Xkb9hJ4MQcGChPSwV6r4t0NDY5ptWljI7Jojd6VPkzqFuSS2RbWFuqyH2Ne kp+Q== X-Gm-Message-State: AC+VfDwrghkkMAa5TUNhRn01WWbVFrnIJnd/espjTl+/K646FkQIWs7C EvAEmhifgEfmgJ3NM3fZBtdOE/Qw0qKkJd+wYN8= X-Received: by 2002:a17:907:2e0b:b0:992:1308:f551 with SMTP id ig11-20020a1709072e0b00b009921308f551mr117254ejc.9.1687821635934; Mon, 26 Jun 2023 16:20:35 -0700 (PDT) Received: from m1x-phil.lan ([176.187.199.226]) by smtp.gmail.com with ESMTPSA id rn19-20020a170906d93300b0098822e05eddsm3753487ejb.100.2023.06.26.16.20.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 26 Jun 2023 16:20:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bin Meng , Liu Zhiwei , =?utf-8?q?Alex_Benn=C3=A9e?= , Thomas Huth , Beraldo Leal , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Dau?= =?utf-8?q?d=C3=A9?= , Palmer Dabbelt , Wainer dos Santos Moschetta , Daniel Henrique Barboza , Weiwei Li , qemu-riscv@nongnu.org Subject: [PATCH 04/16] target/riscv: Restrict 'rv128' machine to TCG accelerator Date: Tue, 27 Jun 2023 01:19:55 +0200 Message-Id: <20230626232007.8933-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230626232007.8933-1-philmd@linaro.org> References: <20230626232007.8933-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::630; envelope-from=philmd@linaro.org; helo=mail-ej1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only build for 32/64-bit hosts, so TCG is required for 128-bit targets. Signed-off-by: Philippe Mathieu-Daudé --- target/riscv/cpu.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 175dbc9826..7f281cdcf6 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -473,6 +473,7 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } +#ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { if (qemu_tcg_mttcg_enabled()) { @@ -491,7 +492,10 @@ static void rv128_base_cpu_init(Object *obj) set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV57); #endif } -#else +#endif + +#else /* !TARGET_RISCV64 */ + static void rv32_base_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; @@ -573,7 +577,7 @@ static void rv32_imafcu_nommu_cpu_init(Object *obj) cpu->cfg.ext_icsr = true; cpu->cfg.pmp = true; } -#endif +#endif /* !TARGET_RISCV64 */ #if defined(CONFIG_KVM) static void riscv_host_cpu_init(Object *obj) @@ -1947,8 +1951,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_CPU(TYPE_RISCV_CPU_SHAKTI_C, rv64_sifive_u_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_THEAD_C906, rv64_thead_c906_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_VEYRON_V1, rv64_veyron_v1_cpu_init), +#ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, rv128_base_cpu_init), -#endif +#endif /* CONFIG_TCG */ +#endif /* TARGET_RISCV64 */ }; DEFINE_TYPES(riscv_cpu_type_infos)