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[PULL,16/22] target/microblaze: Define TCG_GUEST_DEFAULT_MO

Message ID 20230626153945.76180-17-richard.henderson@linaro.org
State Accepted
Commit f6ff4923b92ceefbe5650c3e90ccdcc57dc60fb7
Headers show
Series [PULL,01/22] accel: Replace target_ulong in tlb_*() | expand

Commit Message

Richard Henderson June 26, 2023, 3:39 p.m. UTC 
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.

This should have been defined when enabling MTTCG.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Fixes: d449561b130 ("configure: microblaze: Enable mttcg")
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/microblaze/cpu.h | 3 +++
 1 file changed, 3 insertions(+)
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Patch

diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h
index 3525de144c..a7b040abd4 100644
--- a/target/microblaze/cpu.h
+++ b/target/microblaze/cpu.h
@@ -24,6 +24,9 @@ 
 #include "exec/cpu-defs.h"
 #include "qemu/cpu-float.h"
 
+/* MicroBlaze is always in-order. */
+#define TCG_GUEST_DEFAULT_MO  TCG_MO_ALL
+
 typedef struct CPUArchState CPUMBState;
 #if !defined(CONFIG_USER_ONLY)
 #include "mmu.h"