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([2602:ae:1598:4c01:b071:df63:5761:f449]) by smtp.gmail.com with ESMTPSA id x25-20020a62fb19000000b0063afb08afeesm1686458pfm.67.2023.06.08.19.24.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Jun 2023 19:24:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ardb@kernel.org, berrange@redhat.com, qemu-ppc@nongnu.org, qemu-arm@nongnu.org, qemu-riscv@nongnu.org, pbonzini@redhat.com Subject: [PATCH v2 06/38] crypto: Add aesenc_SB_SR_AK Date: Thu, 8 Jun 2023 19:23:29 -0700 Message-Id: <20230609022401.684157-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230609022401.684157-1-richard.henderson@linaro.org> References: <20230609022401.684157-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::32d; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Start adding infrastructure for accelerating guest AES. Begin with a SubBytes + ShiftRows + AddRoundKey primitive. Signed-off-by: Richard Henderson --- host/include/generic/host/aes-round.h | 16 ++++++++++ include/crypto/aes-round.h | 44 +++++++++++++++++++++++++++ crypto/aes.c | 44 +++++++++++++++++++++++++++ 3 files changed, 104 insertions(+) create mode 100644 host/include/generic/host/aes-round.h create mode 100644 include/crypto/aes-round.h diff --git a/host/include/generic/host/aes-round.h b/host/include/generic/host/aes-round.h new file mode 100644 index 0000000000..19c8505e2b --- /dev/null +++ b/host/include/generic/host/aes-round.h @@ -0,0 +1,16 @@ +/* + * No host specific aes acceleration. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef GENERIC_HOST_AES_ROUND_H +#define GENERIC_HOST_AES_ROUND_H + +#define HAVE_AES_ACCEL false +#define ATTR_AES_ACCEL + +void aesenc_SB_SR_AK_accel(AESState *, const AESState *, + const AESState *, bool) + QEMU_ERROR("unsupported accel"); + +#endif diff --git a/include/crypto/aes-round.h b/include/crypto/aes-round.h new file mode 100644 index 0000000000..15ea1f42bc --- /dev/null +++ b/include/crypto/aes-round.h @@ -0,0 +1,44 @@ +/* + * AES round fragments, generic version + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2023 Linaro, Ltd. + */ + +#ifndef CRYPTO_AES_ROUND_H +#define CRYPTO_AES_ROUND_H + +/* Hosts with acceleration will usually need a 16-byte vector type. */ +typedef uint8_t AESStateVec __attribute__((vector_size(16))); + +typedef union { + uint8_t b[16]; + uint32_t w[4]; + uint64_t d[4]; + AESStateVec v; +} AESState; + +#include "host/aes-round.h" + +/* + * Perform SubBytes + ShiftRows. + */ + +void aesenc_SB_SR_AK_gen(AESState *ret, const AESState *st, + const AESState *rk); +void aesenc_SB_SR_AK_genrev(AESState *ret, const AESState *st, + const AESState *rk); + +static inline void aesenc_SB_SR_AK(AESState *r, const AESState *st, + const AESState *rk, bool be) +{ + if (HAVE_AES_ACCEL) { + aesenc_SB_SR_AK_accel(r, st, rk, be); + } else if (HOST_BIG_ENDIAN == be) { + aesenc_SB_SR_AK_gen(r, st, rk); + } else { + aesenc_SB_SR_AK_genrev(r, st, rk); + } +} + +#endif /* CRYPTO_AES_ROUND_H */ diff --git a/crypto/aes.c b/crypto/aes.c index cdf937883d..896f6f44f1 100644 --- a/crypto/aes.c +++ b/crypto/aes.c @@ -29,6 +29,7 @@ */ #include "qemu/osdep.h" #include "crypto/aes.h" +#include "crypto/aes-round.h" typedef uint32_t u32; typedef uint8_t u8; @@ -1249,6 +1250,49 @@ static const u32 rcon[] = { 0x1B000000, 0x36000000, /* for 128-bit blocks, Rijndael never uses more than 10 rcon values */ }; +/* Perform SubBytes + ShiftRows + AddRoundKey. */ +static inline void +aesenc_SB_SR_AK_swap(AESState *ret, const AESState *st, + const AESState *rk, bool swap) +{ + const int swap_b = swap ? 15 : 0; + AESState t; + + t.b[swap_b ^ 0x0] = AES_sbox[st->b[swap_b ^ AES_SH_0]]; + t.b[swap_b ^ 0x1] = AES_sbox[st->b[swap_b ^ AES_SH_1]]; + t.b[swap_b ^ 0x2] = AES_sbox[st->b[swap_b ^ AES_SH_2]]; + t.b[swap_b ^ 0x3] = AES_sbox[st->b[swap_b ^ AES_SH_3]]; + t.b[swap_b ^ 0x4] = AES_sbox[st->b[swap_b ^ AES_SH_4]]; + t.b[swap_b ^ 0x5] = AES_sbox[st->b[swap_b ^ AES_SH_5]]; + t.b[swap_b ^ 0x6] = AES_sbox[st->b[swap_b ^ AES_SH_6]]; + t.b[swap_b ^ 0x7] = AES_sbox[st->b[swap_b ^ AES_SH_7]]; + t.b[swap_b ^ 0x8] = AES_sbox[st->b[swap_b ^ AES_SH_8]]; + t.b[swap_b ^ 0x9] = AES_sbox[st->b[swap_b ^ AES_SH_9]]; + t.b[swap_b ^ 0xa] = AES_sbox[st->b[swap_b ^ AES_SH_A]]; + t.b[swap_b ^ 0xb] = AES_sbox[st->b[swap_b ^ AES_SH_B]]; + t.b[swap_b ^ 0xc] = AES_sbox[st->b[swap_b ^ AES_SH_C]]; + t.b[swap_b ^ 0xd] = AES_sbox[st->b[swap_b ^ AES_SH_D]]; + t.b[swap_b ^ 0xe] = AES_sbox[st->b[swap_b ^ AES_SH_E]]; + t.b[swap_b ^ 0xf] = AES_sbox[st->b[swap_b ^ AES_SH_F]]; + + /* + * Perform the AddRoundKey with generic vectors. + * This may be expanded to either host integer or host vector code. + * The key and output endianness match, so no bswap required. + */ + ret->v = t.v ^ rk->v; +} + +void aesenc_SB_SR_AK_gen(AESState *r, const AESState *s, const AESState *k) +{ + aesenc_SB_SR_AK_swap(r, s, k, false); +} + +void aesenc_SB_SR_AK_genrev(AESState *r, const AESState *s, const AESState *k) +{ + aesenc_SB_SR_AK_swap(r, s, k, true); +} + /** * Expand the cipher key into the encryption key schedule. */