diff mbox series

[PULL,31/52] exec-all: Widen tb_page_addr_t for user-only

Message ID	20230605201548.1596865-32-richard.henderson@linaro.org
State	Accepted
Commit	087e2341fbf064b4de47b964670110f4d4642cd3
Headers	show Delivered-To: patch@linaro.org Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; From: Richard Henderson <richard.henderson@linaro.org> To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <philmd@linaro.org> Subject: [PULL 31/52] exec-all: Widen tb_page_addr_t for user-only Date: Mon, 5 Jun 2023 13:15:27 -0700 Message-Id: <20230605201548.1596865-32-richard.henderson@linaro.org> In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org
Series	[PULL,01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL \| expand [PULL,01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL [PULL,02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL [PULL,03/52] tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL [PULL,04/52] tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL [PULL,05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h [PULL,06/52] tcg: Widen CPUTLBEntry comparators to 64-bits [PULL,07/52] tcg: Add tlb_fast_offset to TCGContext [PULL,08/52] target/avr: Add missing includes of qemu/error-report.h [PULL,09/52] target/: Add missing includes of tcg/debug-assert.h [PULL,10/52] : Add missing includes of tcg/tcg.h [PULL,11/52] tcg: Split out tcg-target-reg-bits.h [PULL,12/52] target/arm: Fix test of TCG_OVERSIZED_GUEST [PULL,13/52] tcg: Split out tcg/oversized-guest.h [PULL,14/52] tcg: Move TCGv, dup_const_tl definitions to tcg-op.h [PULL,15/52] tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h [PULL,16/52] target/arm: Include helper-gen.h in translator.h [PULL,17/52] target/hexagon: Include helper-gen.h where needed [PULL,18/52] tcg: Remove outdated comments in helper-head.h [PULL,19/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h [PULL,20/52] tcg: Pass TCGHelperInfo to tcg_gen_callN [PULL,21/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line [PULL,22/52] tcg: Split tcg_gen_callN [PULL,23/52] tcg: Split helper-gen.h [PULL,24/52] tcg: Split helper-proto.h [PULL,25/52] target/sh4: Emit insn_start for each insn in gUSA region [PULL,26/52] tcg: Add insn_start_words to TCGContext [PULL,27/52] tcg: Add guest_mo to TCGContext [PULL,28/52] tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits [PULL,29/52] tcg: Split tcg/tcg-op-gvec.h [PULL,30/52] tcg: Remove NO_CPU_IO_DEFS [PULL,31/52] exec-all: Widen tb_page_addr_t for user-only [PULL,32/52] exec-all: Widen TranslationBlock pc and cs_base to 64-bits [PULL,33/52] tcg: Spit out exec/translation-block.h [PULL,34/52] include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE [PULL,35/52] accel/tcg: Move most of gen-icount.h into translator.c [PULL,36/52] accel/tcg: Introduce translator_io_start [PULL,37/52] target/ppc: Inline gen_icount_io_start() [PULL,38/52] accel/tcg: Move translator_fake_ldb out of line [PULL,39/52] target/arm: Tidy helpers for translation [PULL,40/52] target/mips: Tidy helpers for translation [PULL,41/52] target/*: Add missing includes of exec/translation-block.h [PULL,42/52] target/arm: Add missing include of exec/exec-all.h [PULL,43/52] accel/tcg: Tidy includes for translator.[ch] [PULL,44/52] tcg: Fix PAGE/PROT confusion [PULL,45/52] tcg: Move env defines out of NEED_CPU_H in helper-head.h [PULL,46/52] tcg: Remove target-specific headers from tcg.[ch] [PULL,47/52] plugins: Move plugin_insn_append to translator.c [PULL,48/52] plugins: Drop unused headers from exec/plugin-gen.h [PULL,49/52] exec/poison: Do not poison CONFIG_SOFTMMU [PULL,50/52] tcg: Build once for system and once for user-only [PULL,51/52] accel/tcg: Unmap perf_marker [PULL,52/52] tcg/tcg-op-vec: Remove left over _link_error() definitions

Commit Message

Richard Henderson June 5, 2023, 8:15 p.m. UTC

This is a step toward making TranslationBlock agnostic
to the address size of the guest.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 include/exec/exec-all.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff mbox series

Patch

diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index 3b1b57f6ad..ec0902c532 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -31,8 +31,8 @@ 
    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
    type.  */
 #if defined(CONFIG_USER_ONLY)
-typedef abi_ulong tb_page_addr_t;
-#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx
+typedef vaddr tb_page_addr_t;
+#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx
 #else
 typedef ram_addr_t tb_page_addr_t;
 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT