From patchwork Thu May 25 23:25:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 685637 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp623380wrt; Thu, 25 May 2023 16:28:36 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4KiCz6qfUEqRRyUn3S6mHas0lRHidju2o/K3xR8pzZzmcqndzXW5UtouY3pvy/PKnFitbl X-Received: by 2002:a05:622a:1804:b0:3f7:f9c6:d33a with SMTP id t4-20020a05622a180400b003f7f9c6d33amr112838qtc.51.1685057315966; Thu, 25 May 2023 16:28:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685057315; cv=none; d=google.com; s=arc-20160816; b=ajMGJQit5HTWbksAeIXPFuB4MoyD30GV8132jL2O33t6fwl7sK1KKeWZrSu9gD6pjX xY0aJifFMZG3XTy9KjO4L9rKjQUodyrpXXLVLhNs9OrdyXFs89gHlObEWVxyGV5gkoQl Lu2ecalzNXZAn5FSHpp+hYupTkgKAEhYP7YGcmhscA6px2h1hokRTDzCZ+vLJi91Kbue tRIv14XZtB0MEtW7V2QZswzrFzXIEdDvKOFcGKulCQMgxi/wIV7CENxFMXpioDHs2LjP tE88TUZM4EAF1wiemVBZwm9A9kWK0VGU1sIXsutBDkjrheE81zPXK/+AMEoXiVfSjY6f yZGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=DQ7LS6GO0xn5SOg+LgvLn798Ax1iUVpOwdN+LyjqasOR2EUh0rJPBbbStVyKhbnZTt Q/D07+FmYH4fkSEihJLcJbB4wnEJpEAlFg9uPeEVz3GDPc09WL4s8tuLKPkaRS+X73oU lol5dIk2RZNqK9fcioubT5IqUBXIRB5ROc6xeEuz+ucK1NKdDPBEH2ca4b8d0+enSsk7 4+Xs6EJGwIGyezPFgpyQ0I1Mj3/kjILCzJMJbEcWwnq/2PNov3Tw/zUQS/3dUKh+0oWS Ho5YCy2Wnme5E9f4vmos6JBfqLWDrRykJDg9y7yFsZKuwp5UlWd7q75c/GjlmtCBzz6j Pqxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s9bev9Ez; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t2-20020a05622a01c200b003f43703b305si875438qtw.714.2023.05.25.16.28.35 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Thu, 25 May 2023 16:28:35 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=s9bev9Ez; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q2KLk-000610-Ue; Thu, 25 May 2023 19:26:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q2KLd-0005v2-T6 for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:24 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q2KLX-0005pq-NZ for qemu-devel@nongnu.org; Thu, 25 May 2023 19:26:21 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-528cdc9576cso84499a12.0 for ; Thu, 25 May 2023 16:26:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685057173; x=1687649173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=s9bev9EzPbIp+avWjI4z0rBnz3v1tsdGaCA1JdAoq23NX0C8oaTaUS9D9hpdB7KVcb 2rQuV1mf/xpygvJBlxdE4M6eMSV16/9MbRRaKjlKDb0aeX+umV0nGcSN13QekHtDp8jd 7sC6IUbxPDRmBA+kcOSh6I4pmg+97EjuwC5kiGCPAf/7CNLUgJ8wWw8g7HyIXTmwr5U0 Ku8ra8HQ2syC9CqNjOT4Y108+wFgUGVlTJQJXV9bv97DdGUUrgWlHszgzStYY5D4PDso 9kZe5V3KjJCuS5CkjmiPBBhZB6MqGTtaD3vJJNHmjXU0juHLv/pSEIL7ZqGojubv8/iN UzwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685057173; x=1687649173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nH2fDEqJMLjGJ94XHGNSezah8PhFABFUd5z9bFsr8bY=; b=Co6uQmlXfFkj0RYtOfG3uvah7oN2THRVs96nMPfhl/xsh/5V6kDATNAjPtLmaxHDd9 4oPWR7muFS843oRtUhF86I8j+WNJwwQ6ilgL2tkJHEGDd4GItm8GrmPrXr04XzFL2dhM N49ztyVYJyTBDOujVHgwk23hBmJn3zNNuzUE8L0kEkccIoXcD0XF0n3sX1uFapqeHEAq m1A211IdXlM4EmMF7gQ5PCfZw8G9tC2xozHQ5bkaxJ9nxoMqvzC/MjJObBUbxTZ+Zxl7 mu9TDYkjjjPYDO68GR7ytzXYI0DmZXTspcDZu3MrNy668+HYmduld6Xdz9ZrGQ+nMiLw oIAg== X-Gm-Message-State: AC+VfDzHJ8dvxrsPxWbV1rkyaOWOYth79RNGhHG6wl0KWr534xmmsy/N iz482Q2/VCyDOq4/8R5sbAsykl73uGh7MmkTNHI= X-Received: by 2002:a17:902:ab5a:b0:1ac:acb5:4336 with SMTP id ij26-20020a170902ab5a00b001acacb54336mr412392plb.33.1685057173345; Thu, 25 May 2023 16:26:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:7ac5:31cc:3997:3a16]) by smtp.gmail.com with ESMTPSA id s15-20020a170902ea0f00b0019e60c645b1sm1885036plg.305.2023.05.25.16.26.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 16:26:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 17/20] target/arm: Move mte check for store-exclusive Date: Thu, 25 May 2023 16:25:55 -0700 Message-Id: <20230525232558.1758967-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230525232558.1758967-1-richard.henderson@linaro.org> References: <20230525232558.1758967-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Push the mte check behind the exclusive_addr check. Document the several ways that we are still out of spec with this implementation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 42 +++++++++++++++++++++++++++++----- 1 file changed, 36 insertions(+), 6 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 49cb7a7dd5..9654c5746a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2524,17 +2524,47 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, */ TCGLabel *fail_label = gen_new_label(); TCGLabel *done_label = gen_new_label(); - TCGv_i64 tmp, dirty_addr, clean_addr; + TCGv_i64 tmp, clean_addr; MemOp memop; - memop = (size + is_pair) | MO_ALIGN; - memop = finalize_memop(s, memop); - - dirty_addr = cpu_reg_sp(s, rn); - clean_addr = gen_mte_check1(s, dirty_addr, true, rn != 31, memop); + /* + * FIXME: We are out of spec here. We have recorded only the address + * from load_exclusive, not the entire range, and we assume that the + * size of the access on both sides match. The architecture allows the + * store to be smaller than the load, so long as the stored bytes are + * within the range recorded by the load. + */ + /* See AArch64.ExclusiveMonitorsPass() and AArch64.IsExclusiveVA(). */ + clean_addr = clean_data_tbi(s, cpu_reg_sp(s, rn)); tcg_gen_brcond_i64(TCG_COND_NE, clean_addr, cpu_exclusive_addr, fail_label); + /* + * The write, and any associated faults, only happen if the virtual + * and physical addresses pass the exclusive monitor check. These + * faults are exceedingly unlikely, because normally the guest uses + * the exact same address register for the load_exclusive, and we + * would have recognized these faults there. + * + * It is possible to trigger an alignment fault pre-LSE2, e.g. with an + * unaligned 4-byte write within the range of an aligned 8-byte load. + * With LSE2, the store would need to cross a 16-byte boundary when the + * load did not, which would mean the store is outside the range + * recorded for the monitor, which would have failed a corrected monitor + * check above. For now, we assume no size change and retain the + * MO_ALIGN to let tcg know what we checked in the load_exclusive. + * + * It is possible to trigger an MTE fault, by performing the load with + * a virtual address with a valid tag and performing the store with the + * same virtual address and a different invalid tag. + */ + memop = size + is_pair; + if (memop == MO_128 || !dc_isar_feature(aa64_lse2, s)) { + memop |= MO_ALIGN; + } + memop = finalize_memop(s, memop); + gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn != 31, memop); + tmp = tcg_temp_new_i64(); if (is_pair) { if (size == 2) {