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([2602:ae:1598:4c01:c13a:d73:4f88:3654]) by smtp.gmail.com with ESMTPSA id b8-20020aa78708000000b0064d27a28451sm5796111pfo.100.2023.05.23.06.53.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 May 2023 06:53:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h Date: Tue, 23 May 2023 06:52:35 -0700 Message-Id: <20230523135322.678948-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230523135322.678948-1-richard.henderson@linaro.org> References: <20230523135322.678948-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Removes the only use of TARGET_LONG_BITS from tcg.h, which is to be target independent. Move the symbol to a define in tcg-op.h, which will continue to be target dependent. Rather than complicate matters for the use in tb_gen_code(), expand the definition there. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/tcg/tcg-op.h | 8 ++++++++ include/tcg/tcg.h | 7 ------- accel/tcg/translate-all.c | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 35c5700183..844c666374 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -722,6 +722,14 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) #error must include QEMU headers #endif +#if TARGET_LONG_BITS == 32 +# define TCG_TYPE_TL TCG_TYPE_I32 +#elif TARGET_LONG_BITS == 64 +# define TCG_TYPE_TL TCG_TYPE_I64 +#else +# error +#endif + #if TARGET_INSN_START_WORDS == 1 static inline void tcg_gen_insn_start(target_ulong pc) { diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 072c35f7f5..0da17f1b4f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -292,13 +292,6 @@ typedef enum TCGType { #else TCG_TYPE_PTR = TCG_TYPE_I64, #endif - - /* An alias for the size of the target "long", aka register. */ -#if TARGET_LONG_BITS == 64 - TCG_TYPE_TL = TCG_TYPE_I64, -#else - TCG_TYPE_TL = TCG_TYPE_I32, -#endif } TCGType; /** diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 353849ca6d..f6c8ad1a18 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -356,7 +356,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); tcg_ctx->gen_tb = tb; - tcg_ctx->addr_type = TCG_TYPE_TL; + tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64; #ifdef CONFIG_SOFTMMU tcg_ctx->page_bits = TARGET_PAGE_BITS; tcg_ctx->page_mask = TARGET_PAGE_MASK;