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[176.184.48.94]) by smtp.gmail.com with ESMTPSA id n1-20020a05600c294100b003ee74c25f12sm13828813wmd.35.2023.05.22.23.44.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 22 May 2023 23:44:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , qemu-ppc@nongnu.org, Titus Rwantare , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH 1/3] hw/mips/jazz: Fix modifying QOM class internal state from instance Date: Tue, 23 May 2023 08:44:06 +0200 Message-Id: <20230523064408.57941-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230523064408.57941-1-philmd@linaro.org> References: <20230523064408.57941-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QOM object instance should not modify its class state (because all other objects instanciated from this class get affected). Instead of modifying the MIPSCPUClass 'no_data_aborts' field in the instance machine_init() handler, set it in the machine class_init handler. Since 2 machines require this, share the common code in a new machine_class_ignore_data_abort() helper. Inspired-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/jazz.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index ca4426a92c..de2e827bf8 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -128,7 +128,6 @@ static void mips_jazz_init(MachineState *machine, int bios_size, n, big_endian; Clock *cpuclk; MIPSCPU *cpu; - MIPSCPUClass *mcc; CPUMIPSState *env; qemu_irq *i8259; rc4030_dma *dmas; @@ -177,23 +176,6 @@ static void mips_jazz_init(MachineState *machine, env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); - /* - * Chipset returns 0 in invalid reads and do not raise data exceptions. - * However, we can't simply add a global memory region to catch - * everything, as this would make all accesses including instruction - * accesses be ignored and not raise exceptions. - * - * NOTE: this behaviour of raising exceptions for bad instruction - * fetches but not bad data accesses was added in commit 54e755588cf1e9 - * to restore behaviour broken by c658b94f6e8c206, but it is not clear - * whether the real hardware behaves this way. It is possible that - * real hardware ignores bad instruction fetches as well -- if so then - * we could replace this hijacking of CPU methods with a simple global - * memory region that catches all memory accesses, as we do on Malta. - */ - mcc = MIPS_CPU_GET_CLASS(cpu); - mcc->no_data_aborts = true; - /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); @@ -414,6 +396,27 @@ void mips_pica61_init(MachineState *machine) mips_jazz_init(machine, JAZZ_PICA61); } +static void machine_class_ignore_data_abort(MachineClass *mc) +{ + MIPSCPUClass *mcc = MIPS_CPU_CLASS(mc); + + /* + * Chipset returns 0 in invalid reads and do not raise data exceptions. + * However, we can't simply add a global memory region to catch + * everything, as this would make all accesses including instruction + * accesses be ignored and not raise exceptions. + * + * NOTE: this behaviour of raising exceptions for bad instruction + * fetches but not bad data accesses was added in commit 54e755588cf1e9 + * to restore behaviour broken by c658b94f6e8c206, but it is not clear + * whether the real hardware behaves this way. It is possible that + * real hardware ignores bad instruction fetches as well -- if so then + * we could replace this hijacking of CPU methods with a simple global + * memory region that catches all memory accesses, as we do on Malta. + */ + mcc->no_data_aborts = true; +} + static void mips_magnum_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -423,6 +426,7 @@ static void mips_magnum_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_SCSI; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); mc->default_ram_id = "mips_jazz.ram"; + machine_class_ignore_data_abort(mc); } static const TypeInfo mips_magnum_type = { @@ -440,6 +444,7 @@ static void mips_pica61_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_SCSI; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); mc->default_ram_id = "mips_jazz.ram"; + machine_class_ignore_data_abort(mc); } static const TypeInfo mips_pica61_type = {